Patents by Inventor Shyng-Tsong Chen
Shyng-Tsong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10672984Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.Type: GrantFiled: May 16, 2019Date of Patent: June 2, 2020Assignee: International Business Machines CorporationInventors: Takashi Ando, Michael Rizzolo, Lawrence A. Clevenger, Shyng-Tsong Chen
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Publication number: 20200028080Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.Type: ApplicationFiled: May 16, 2019Publication date: January 23, 2020Inventors: Takashi Ando, Michael Rizzolo, Lawrence A. Clevenger, Shyng-Tsong Chen
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Publication number: 20200028076Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.Type: ApplicationFiled: May 2, 2019Publication date: January 23, 2020Inventors: Takashi Ando, Hiroyuki Miyazoe, Iqbal R. Saraf, Shyng-Tsong Chen
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Publication number: 20190318989Abstract: In accordance with an embodiment of the present invention, a photolithographic mask is provided. The photolithographic mask includes at least one merged via pattern in the photolithographic mask for printing a merged via opening in a resist layer, wherein the at least one merged via pattern includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.Type: ApplicationFiled: April 12, 2018Publication date: October 17, 2019Inventors: Dongbing Shao, Lawrence A. Clevenger, Shyng-Tsong Chen, Hao Tang, Jing Sha
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Patent number: 10381563Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.Type: GrantFiled: July 17, 2018Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: Takashi Ando, Michael Rizzolo, Lawrence A. Clevenger, Shyng-Tsong Chen
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Patent number: 10361367Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.Type: GrantFiled: July 17, 2018Date of Patent: July 23, 2019Assignee: International Business Machines CorporationInventors: Takashi Ando, Hiroyuki Miyazoe, Iqbal R. Saraf, Shyng-Tsong Chen
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Patent number: 10157789Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.Type: GrantFiled: August 17, 2016Date of Patent: December 18, 2018Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, INC., STMicroelectronics, Inc.Inventors: Shyng-Tsong Chen, Cheng Chi, Chi-Chun Liu, Sylvie M. Mignot, Yann A. Mignot, Hosadurga K. Shobha, Terry A. Spooner, Wenhui Wang, Yongan Xu
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Publication number: 20160358820Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.Type: ApplicationFiled: August 17, 2016Publication date: December 8, 2016Inventors: Shyng-Tsong Chen, Cheng Chi, Chi-Chun Liu, Sylvie M. Mignot, Yann A. Mignot, Hosadurga K. Shobha, Terry A. Spooner, Wenhui Wang, Yongan Xu
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Patent number: 9508647Abstract: A single damascene interconnect structure which includes a first layer that includes a first dielectric material having a first filled opening that has a barrier layer of a refractory material with Cu filling the first filled opening. Also included is a second layer of a second dielectric material having a second filled opening that has a sidewall layer which includes a compound of a metal, O, and Si such that the metal is Mn, Ti and Al, and with Cu filling the second filled opening. The compound is in direct contact with the second dielectric material. The first layer is adjacent to the second layer and the first filled opening is aligned with the second filled opening so that the first filled opening is a via and the second filled opening is a trench.Type: GrantFiled: October 20, 2015Date of Patent: November 29, 2016Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Daniel C. Edelstein, Takeshi Nogami
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Publication number: 20160336225Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.Type: ApplicationFiled: May 13, 2015Publication date: November 17, 2016Inventors: Shyng-Tsong Chen, Cheng Chi, Chi-Chun Liu, Sylvie M. Mignot, Yann A. Mignot, Hosadurga K. Shobha, Terry A. Spooner, Wenhui Wang, Yongan Xu
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Patent number: 9490168Abstract: A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.Type: GrantFiled: May 13, 2015Date of Patent: November 8, 2016Assignees: International Business Machines Corporation, GlobalFoundries, Inc., STMicroelectronics, Inc.Inventors: Shyng-Tsong Chen, Cheng Chi, Chi-Chun Liu, Sylvie M. Mignot, Yann A. Mignot, Hosadurga K. Shobha, Terry A. Spooner, Wenhui Wang, Yongan Xu
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Publication number: 20160071802Abstract: A single damascene interconnect structure which includes a first layer that includes a first dielectric material having a first filled opening that has a barrier layer of a refractory material with Cu filling the first filled opening. Also included is a second layer of a second dielectric material having a second filled opening that has a sidewall layer which includes a compound of a metal, O, and Si such that the metal is Mn, Ti and Al, and with Cu filling the second filled opening. The compound is in direct contact with the second dielectric material. The first layer is adjacent to the second layer and the first filled opening is aligned with the second filled opening so that the first filled opening is a via and the second filled opening is a trench.Type: ApplicationFiled: October 20, 2015Publication date: March 10, 2016Inventors: Shyng-Tsong Chen, Daniel C. Edelstein, Takeshi Nogami
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Patent number: 9224686Abstract: A single damascene interconnect structure which includes a first layer of a first dielectric material having a first filled opening that has a sidewall layer which includes a compound of a metal, O, and Si such that the metal is Mn, Ti and Al, and with Cu filling the first filled opening. The compound is in direct contact with the first dielectric material. Also included is a second layer that includes a second dielectric material having a second filled opening that has a barrier layer of a refractory material with Cu filling the second filled opening. The first layer is adjacent to the second layer and the first filled opening is aligned with the second filled opening so that one of the first and second filled openings is a via and the other of the first and second filled openings is a trench.Type: GrantFiled: September 10, 2014Date of Patent: December 29, 2015Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Daniel C. Edelstein, Takeshi Nogami
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Patent number: 9105641Abstract: The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.Type: GrantFiled: September 15, 2014Date of Patent: August 11, 2015Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Wai-Kin Li, Christopher J. Penny, Shom Ponoth, Chih-Chao Yang, Yunpeng Yin
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Publication number: 20150221547Abstract: A stack of an interlevel dielectric (ILD) layer, a dielectric cap layer, and a metallic hard mask layer is formed on a substrate. The metallic hard mask layer can be patterned with a first pattern. A photoresist layer is formed over the metallic hard mask layer and is patterned with a second pattern. A combination of the first pattern and the second pattern is transferred into the ILD layer to form a dual damascene trench, which includes an undercut underneath the patterned dielectric cap layer. The metallic hard mask layer is removed and the dielectric cap layer is anisotropically etched to form faceted edges and removal of overhanging portions. A metallic material can be deposited into the dual damascene trench without formation of voids during a metal fill process.Type: ApplicationFiled: February 4, 2014Publication date: August 6, 2015Applicants: STMICROELECTRONIC, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John C. Arnold, Shyng-Tsong Chen, Yann Mignot, Muthumanickam Sankarapandian, Oscar van der Straten, Yunpeng Yin
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Publication number: 20150035154Abstract: The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.Type: ApplicationFiled: September 15, 2014Publication date: February 5, 2015Inventors: Shyng-Tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Wai-Kin Li, Christopher J. Penny, Shom Ponoth, Chih-Chao Yang, Yunpeng Yin
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Publication number: 20140312265Abstract: A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result.Type: ApplicationFiled: July 3, 2014Publication date: October 23, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shyng-Tsong Chen, John A. Fitzsimmons, David L. Rath, Muthumanickam Sankarapandian, Oscar van der Straten
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Patent number: 8835305Abstract: The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.Type: GrantFiled: July 31, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Shyng-Tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Wai-Kin Li, Christopher J. Penny, Shom Ponoth, Yunpeng Yin
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Patent number: 8835326Abstract: A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result.Type: GrantFiled: January 4, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: John A. Fitzsimmons, Shyng-Tsong Chen, David L. Rath, Muthumanickam Sankarapandian, Oscar van der Straten
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Patent number: 8754520Abstract: A microelectronic substrate which includes a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface; a plurality of metal lines of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface of the dielectric layer; a dielectric cap layer having a first portion overlying the surfaces of the metal lines and a second portion overlying the dielectric layer between the metal lines, the first portion has a first height above the surface of the dielectric layer, and the second portion has a second height above the surface of the dielectric layer, the second height being greater than the first height; and an air gap disposed between the metal lines, the air gap underlying the second portion of the cap layer.Type: GrantFiled: January 25, 2013Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Takeshi Nogami, Shyng-Tsong Chen, David V. Horak, Son V. Nguyen, Shom Ponoth, Chih-Chao Yang