Patents by Inventor Shyng-Tsong Chen
Shyng-Tsong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7670943Abstract: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.Type: GrantFiled: July 24, 2008Date of Patent: March 2, 2010Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Griselda Bonilla, Shyng-Tsong Chen, Kelly Malone
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Patent number: 7666753Abstract: The embodiments of the invention provide a metal capping process for a BEOL interconnect with air gaps. More specifically an apparatus is provided comprising metal lines within a first dielectric. Metal caps are over the metal lines, wherein the metal caps contact the metal lines. In addition, air gaps are between the metal lines, wherein the air gaps are between the metal caps. A second dielectric is also provided over the bottom portion of a first dielectric, wherein a top portion of the second dielectric is over the metal caps, and wherein top portions of the first dielectric and bottom portions of the second dielectric comprise sides of the air gap. The apparatus further includes dielectric caps over the metal lines, wherein the dielectric caps contact the metal caps.Type: GrantFiled: January 11, 2007Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Shyng-Tsong Chen, Matthew E. Colburn, Chih-Chao Yang
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Publication number: 20090184400Abstract: Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via.Type: ApplicationFiled: January 21, 2008Publication date: July 23, 2009Applicant: International Business Machines CorporationInventors: Shyng-Tsong Chen, Steven J. Holmes, David V. Horak, Takeshi Nogami, Shom Ponoth, Chih-Chao Yang
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Patent number: 7514361Abstract: A method of creating metal caps on copper lines within an inter-line dielectric (ILD) deposits a thin (e.g., 5 nm) metal blanket film (e.g., Ta/TaN) on top the copper lines and dielectric, after the wafer has been planarized. Further a thin dielectric cap is formed over the metal blanket film. A photoresist coating is deposited over the thin dielectric cap and a lithographic exposure process is performed, but without a lithographic mask. A mask is not needed in this situation, because due to the reflectivity difference between copper and the ILD lying under the two thin layers, a mask pattern is automatically formed for etching away the Ta/TaN metal cap between copper lines. Thus, this mask pattern is self-aligned above the copper lines.Type: GrantFiled: August 20, 2007Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Shyng-Tsong Chen, Matthew E. Colburn, Ronald DellaGuardia, Chih-Chao Yang
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Publication number: 20090079075Abstract: The present invention provides an interconnect structure in which a patternable low-k material is employed as an interconnect dielectric material. Specifically, this invention relates to single-damascene and dual-damascene low-k interconnect structures with at least one patternable low-k dielectric. In general terms, the interconnect structure includes at least one patterned and cured low-k dielectric material located on a surface of a substrate. The at least one cured and patterned low-k material has conductively filled regions embedded therein and typically, but not always, includes Si atoms bonded to cyclic rings via oxygen atoms. The present invention also provides a method of forming such interconnect structures in which no separate photoresist is employed in patterning the patterned low-k material.Type: ApplicationFiled: September 20, 2007Publication date: March 26, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Qinghuang Lin, Shyng-Tsong Chen
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Publication number: 20090053890Abstract: A method of creating metal caps on copper lines within an inter-line dielectric (ILD) deposits a thin (e.g., 5 nm) metal blanket film (e.g., Ta/TaN) on top the copper lines and dielectric, after the wafer has been planarized. Further a thin dielectric cap is formed over the metal blanket film. A photoresist coating is deposited over the thin dielectric cap and a lithographic exposure process is performed, but without a lithographic mask. A mask is not needed in this situation, because due to the reflectivity difference between copper and the ILD lying under the two thin layers, a mask pattern is automatically formed for etching away the Ta/TaN metal cap between copper lines. Thus, this mask pattern is self-aligned above the copper lines.Type: ApplicationFiled: August 20, 2007Publication date: February 26, 2009Inventors: Griselda Bonilla, Shyng-Tsong Chen, Matthew E. Colburn, Ronald DellaGuardia, Chih-Chao Yang
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Patent number: 7479869Abstract: A metal resistor and resistor material are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The resistor material may include one of: copper (Cu) infused with at least one of silicon (Si), nitrogen (2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W).Type: GrantFiled: October 9, 2007Date of Patent: January 20, 2009Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Kaushik Chanda, Shyng-Tsong Chen
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PROVIDING GAPS IN CAPPING LAYER TO REDUCE TENSILE STRESS FOR BEOL FABRICATION OF INTEGRATED CIRCUITS
Publication number: 20080315347Abstract: Fabricating an integrated circuit using a cap layer that includes one or more gaps or voids. The gaps or voids are provided prior to performing deposition and cure for an inter-layer dielectric (ILD) layer adjoining the cap layer. The gaps or voids reduce and prevent tensile stress buildup by allowing for stress relaxation, hence preventing catastrophic failure of the integrated circuit.Type: ApplicationFiled: June 25, 2007Publication date: December 25, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Shyng-Tsong Chen, Ronald A. DellaGuardia, Qinghuang Lin, Kelly Malone, Shom S. Ponoth, Chih-Chao Yang -
Publication number: 20080284030Abstract: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.Type: ApplicationFiled: July 24, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: Chih-Chao Yang, Griselda Bonilla, Shyng-Tsong Chen, Kelly Malone
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Publication number: 20080280434Abstract: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.Type: ApplicationFiled: July 24, 2008Publication date: November 13, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: CHIH-CHAO YANG, Griselda Bonilla, Shyng-Tsong Chen, Kelly Malone
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Patent number: 7439624Abstract: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.Type: GrantFiled: May 18, 2006Date of Patent: October 21, 2008Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Griselda Bonilla, Shyng-Tsong Chen, Kelly Malone
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Publication number: 20080242082Abstract: A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place.Type: ApplicationFiled: June 12, 2008Publication date: October 2, 2008Inventors: Chih-Chao Yang, Shyng-Tsong Chen, Shom Ponoth, Terry A. Spooner
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Patent number: 7402883Abstract: A back end of the line (BEOL) structure of a semiconductor device is presented. In one embodiment, the structure may include a first liner layer disposed on an intermediate interconnect structure, the intermediate interconnect structure having an opening disposed between two surfaces of a dielectric material, wherein the first liner layer is in direct contact with at least a portion of a conductive wiring material of an underneath interconnect layer; a noble metal layer disposed on the first liner layer at least in the opening; and a conductive wiring material disposed on the noble metal layer, the conductive wiring material substantially filling the opening; wherein the first liner layer, the noble metal layer and the conductive wiring material are coplanar with the two surfaces of the dielectric material of the intermediate interconnect structure, and the noble metal layer includes a different material than the first liner layer.Type: GrantFiled: April 25, 2006Date of Patent: July 22, 2008Assignee: International Business Machines Corporation, Inc.Inventors: Chih-Chao Yang, Shyng-Tsong Chen, Shom Ponoth, Terry A. Spooner
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Publication number: 20080169565Abstract: The embodiments of the invention provide a metal capping process for a BEOL interconnect with air gaps. More specifically an apparatus is provided comprising metal lines within a first dielectric. Metal caps are over the metal lines, wherein the metal caps contact the metal lines. In addition, air gaps are between the metal lines, wherein the air gaps are between the metal caps. A second dielectric is also provided over the bottom portion of a first dielectric, wherein a top portion of the second dielectric is over the metal caps, and wherein top portions of the first dielectric and bottom portions of the second dielectric comprise sides of the air gap. The apparatus further includes dielectric caps over the metal lines, wherein the dielectric caps contact the metal caps.Type: ApplicationFiled: January 11, 2007Publication date: July 17, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Shyng-Tsong Chen, Matthew E. Colburn, Chih-Chao Yang
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Publication number: 20080146029Abstract: A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and plasma photoresist removal processes and performing one or more additional plasma etch processes that do not include oxygen containing species to etch the openings to depths required for forming the damascene interconnect structures and to remove any organo-silicate material damaged by the combination of plasma etch and plasma photoresist removal processes.Type: ApplicationFiled: February 20, 2008Publication date: June 19, 2008Inventors: Heidi Lee Baks, Shyng-Tsong Chen, Timothy Joseph Dalton, Nicholas Colvin Masi Fuller
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Publication number: 20080090402Abstract: A method of fabricating and a structure of an integrated circuit (IC) incorporating a porous dielectric layer are disclosed. A metal line is formed in the porous dielectric layer. A gas cluster ion beam process is applied to the porous dielectric layer so that an upper portion of the dielectric layer is densified to be not porous or non-interconnected low porous, while a lower portion of the porous dielectric layer still maintains its ultra-low dielectric constant after the gas cluster ion beam process.Type: ApplicationFiled: September 29, 2006Publication date: April 17, 2008Inventors: Griselda Bonilla, Shyng-Tsong Chen, John A. Fitzsimmons, Sanjay Mehta, Shom Ponoth
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Patent number: 7358182Abstract: A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and plasma photoresist removal processes and performing one or more additional plasma etch processes that do not include oxygen containing species to etch the openings to depths required for forming the damascene interconnect structures and to remove any organo-silicate material damaged by the combination of plasma etch and plasma photoresist removal processes.Type: GrantFiled: December 22, 2005Date of Patent: April 15, 2008Assignee: International Business Machines CorporationInventors: Heidi Lee Baks, Shyng-Tsong Chen, Timothy Joseph Dalton, Nicholas Colvin Masi Fuller, Kaushik Arun Kumar
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Patent number: 7341948Abstract: Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and PEL, and then plating copper on the seed layer. The PEL serves to decrease the resistance across the wafer so to facilitate the plating of the copper. The PEL preferably is an optically transparent and conductive layer.Type: GrantFiled: January 17, 2006Date of Patent: March 11, 2008Assignee: International Business Machines CorporationInventors: Shom Ponoth, Steven Shyng-Tsong Chen, John Anthony Fitzsimmons, Terry Allen Spooner
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Patent number: 7314786Abstract: A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The method is less complex than conventional processes, allows control of the resistance by the amount of infusion material infused, and is compatible with conventional BEOL processes.Type: GrantFiled: June 16, 2006Date of Patent: January 1, 2008Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Kaushik Chanda, Shyng-Tsong Chen
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Publication number: 20070293000Abstract: A metal resistor and resistor material and method of forming the metal resistor are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The method is less complex than conventional processes, allows control of the resistance by the amount of infusion material infused, and is compatible with conventional BEOL processes.Type: ApplicationFiled: June 16, 2006Publication date: December 20, 2007Inventors: Chih-Chao Yang, Kaushik Chanda, Shyng-Tsong Chen