Abstract: The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.

Abstract: A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place.

Abstract: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom and/or sidewall of the trench and/or via is usually damaged by a following metallization or cleaning process which may be suitable for dense higher dielectric materials. Embodiments of the present invention may provide a method of repairing process induced dielectric damage from forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes treating an exposed area of the ILD material to create a carbon-rich area, and metallizing the carbon-rich area. One embodiment includes providing treatment to an exposed sidewall area of the ILD material to create a carbon-rich area by irradiating the exposed area using a gas cluster ion beam (GCIB) generated through a gas including a straight chain or branched, aliphatic or aromatic hydrocarbon, and metallizing the carbon-rich area.

Abstract: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.

Abstract: A method of forming damascene interconnect structure in an organo-silicate glass layer without causing damage to the organo-silicate glass material. The method includes forming a stack of hardmask layers over the organo-silicate glass layer, defining openings in the hardmask and organo-silicate glass layers using a combination of plasma etch and plasma photoresist removal processes and performing one or more additional plasma etch processes that do not include oxygen containing species to etch the openings to depths required for forming the damascene interconnect structures and to remove any organo-silicate material damaged by the combination of plasma etch and plasma photoresist removal processes.

Abstract: A method comprises depositing a dielectric film layer, a hard mask layer, and a patterned photo resist layer on a substrate. The method further includes selectively etching the dielectric film layer to form sub-lithographic features by reactive ion etch processing and depositing a barrier metal layer and a copper layer. The method further includes etching the barrier metal layer and hard mask layer by gas cluster ion beam (GCIB) processing.

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract: A polishing pad having a body comprising fibers embedded in a matrix polymer formed by a reaction of polymer precursors. The loose fibers define and the precursors were mixed first with curatives, then mold into a pad form. The pad may include a thin layer of free fibers at its polishing surface. A segment of at least a portion of the free fibers are embedded in the adjacent body of the polymer and fibers.

Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

Abstract: In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

Abstract: Damaged porous OSG layers and other damage may be chemically healed. Chemical healing is particularly advantageous in a porous OSG layer in a sub 90 nm ILD. For example, chemical healing may be by reacting the damage with an adhesion promoter having a “k” value comparable to the “k” value desired in the damaged material. Damaged porous OSG layers (which are hydrophilic) may be manipulated to prevent them from allowing moisture to reach copper lines. Undesirable copper out-diffusion can be controlled in ILDs having porous OSG geometry.

Abstract: A polishing pad having a body comprising fibers embedded in a matrix polymer formed by a reaction of polymer precursors. The loose fibers define and the precursors were mixed first with curatives, then mold into a pad form. The pad may include a thin layer of free fibers at its polishing surface. A segment of at least a portion of the free fibers are embedded in the adjacent body of the polymer and fibers.

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

Abstract: A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.

Abstract: A method of making a polishing pad having a body comprising fibers embedded in a matrix polymer formed by a reaction of polymer precursors. The fibers define interstices, and the precursors fill these interstices substantially completely before completion of the reaction. The method comprising placing the fibers and the precursors in a cavity of a mold for shaping the polishing pad; applying a differential pressure across a mold cavity, where the differential pressure and the amount of precursors are sufficient to cause the precursors to fill the interstices substantially completely before completion of the reaction; and applying sufficient heat to the mold to at least partially cure the polishing pad by causing the precursors to react.

Abstract: The present invention provides a plastically and/or viscoelastically deformable layer that can be used in conjunction with a low-k dielectric (k of less than 4.0) to provide an electronic semiconductor structure having improved reliability. The deformable layer can be incorporated into various points within an electronic structure to dissipate energy within the structure that may cause the low-k dielectric material to crack or delaminate therefrom. Moreover, the presence of the deformable layer with the electronic structure improves the overall strength of the resultant structure.

Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

Abstract: A polishing pad having a body comprising fibers embedded in a matrix polymer formed by a reaction of polymer precursors. The loose fibers define and the precursors were mixed first with curatives, then mold into a pad form. The pad may include a thin layer of free fibers at its polishing surface. A segment of at least a portion of the free fibers are embedded in the adjacent body of the polymer and fibers.