Abstract: Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor is arranged in series between a termination switch and a common voltage node at the termination end of each bus conductor. Information regarding the current or anticipated bus state is received from an external device such as a bus controller or may be derived by sensing activity on the bus. For example, clock frequency detection logic coupled to clock lines of the bus senses the current operational speed of the bus. A highest-value termination resistance predetermined to be consistent with reliable bus operation under conditions of the current or anticipated bus state is selected for each bus conductor. A bus conductor termination may be taken to a high impedance state by opening the associated termination switch. Decreased average bus power consumption may result.

Abstract: Improved current sensing methods and apparatus and conductor apparatus are presented for sensing current in a bus bar or other conductor using one or more circular magnetic sensors or multiple magnetic sensors disposed on a substrate in a pattern surrounding a longitudinal path within the outer periphery of the conductor to avoid or mitigate sensed magnetic field crosstalk and to facilitate use of high sensitivity magnetic sensors at locations inside the conductor periphery in which the magnetic field is relatively small.

Abstract: Described herein is a system having a multi-host SATA controller (102) configured to provide communication and control between two or more independent host processors (104) and a single SATA device (108). In one implementation, the multi-host SATA controller (102) includes the device switching layer (206), the device control layer (208), the link layer (210), and the physical layer (212). The device switching layer (206) allows the host processors (104) to issue commands concurrently rather than in sequential order. For this, the device switching layer (206) has independent set of host device registers (214) corresponding to each of the host processors (104). The device switching layer (206) also has independent DMA engines (216) to perform a command pre-fetching from respective host system memories (105). Further, a command switch engine (220) may arbitrate commands in case both the host processors (104) wish to access the SATA device (108) simultaneously.

Abstract: A system is provided, comprising: a magnet flux sensor; a first conductor proximate to the magnetic field sensor; a current controller coupled to the first wire; a second conductor proximate to the magnetic field sensor; wherein the first current controller and the second current controller ensure that current do not travel in opposite directions.

Abstract: Improved current sensing methods and apparatus and conductor apparatus are presented for sensing current in a bus bar or other conductor using one or more circular magnetic sensors or multiple magnetic sensors disposed on a substrate in a pattern surrounding a longitudinal path within the outer periphery of the conductor to avoid or mitigate sensed magnetic field crosstalk and to facilitate use of high sensitivity magnetic sensors at locations inside the conductor periphery in which the magnetic field is relatively small.

Abstract: Described herein is a multi-host computing system (100) having multiple host processors running different operating systems. In one implementation, a method of playing audio streams received from a plurality of hosts of a multi-host computing system (100), the method comprising receiving a second audio stream from a second host, and changing audio stream parameters associated with the second audio stream from second host to match the corresponding parameter values associated with a first audio stream received from a first host to generate an updated second audio stream. The method further comprises mixing the updated second audio stream with the first audio stream to generate a combined audio stream, and playing the combined audio stream using at least one audio codec (104) of the multi-host computing system (100).

Abstract: Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor is arranged in series between a termination switch and a common voltage node at the termination end of each bus conductor. Information regarding the current or anticipated bus state is received from an external device such as a bus controller or may be derived by sensing activity on the bus. For example, clock frequency detection logic coupled to clock lines of the bus senses the current operational speed of the bus. A highest-value termination resistance predetermined to be consistent with reliable bus operation under conditions of the current or anticipated bus state is selected for each bus conductor. A bus conductor termination may be taken to a high impedance state by opening the associated termination switch. Decreased average bus power consumption may result.

Abstract: Described herein is a system having a multi-host low pin count (LPC) controller (100) configured to facilitate sharing of common peripheral devices by multiple hosts (115) of a multi-host computing system (110). In one implementation, the multi-host LPC controller (100) interfaces with the hosts (115) via an ON-chip bus or an LPC-IN-chip bus. Further, the multi-host LPC controller (100) includes a LPC-IN controller (160) and a microcontroller (155) to moderate among requests generated by the hosts (115). The requests can be target accesses, DMA accesses, and BM accesses. Also, the multi-host LPC controller (100) is configured to operate in a software mode and an auto mode. Based on the mode the multi-host LPC controller (100) is operating in, the requests generated by the various hosts are moderated.

Abstract: A hierarchical wearable processing unit (HWPU) (102) for WPUs (100) is described. According to an implementation of the present subject matter, the HWPU (102) may include a plurality of hierarchies (106). Each hierarchy (106) from amongst the plurality of hierarchies (106) is determined for a particular performance and power consumption. Further, the HWPU (102) may include a plurality of hosts (104). One or more hosts (104) from amongst the plurality of hosts (104) are associated with each of the plurality of hierarchies (106) based on the particular performance and power consumption of each of the hierarchies (106). Furthermore, the HWPU (102) may include a control unit (118) to configure each of the plurality of hierarchies (106) with functionalities based on allocation of dedicated hardware resources.

Abstract: The present subject matter discloses methods and systems of sharing of peripheral devices in multi host computing systems (100). In one implementation, the method of sharing a peripheral device (116) amongst a plurality of hosts of the multi-host computing system (100) comprises receiving a request to switch the peripheral device (116) from a first operating system running on a first host from amongst the plurality of hosts to a second operating system running on a second host from amongst the plurality of hosts; generating a request for the first operating system to relinquish control of the peripheral device (116); determining the status of the relinquishment based on response generated by the first operating system; initiating a request for the second operating system to install a device driver for the peripheral device (116) upon determining successful relinquishment; and transferring ownership of the peripheral device (116) to the second operating system.

Abstract: Described herein are methods and systems for virtualization of a USB device to enable sharing of the USB device among a plurality of host processors in a multi-processor computing system. A USB virtualization unit for sharing of the USB device include a per-host register unit, each corresponding to a host processor includes one or more of a host register interface, host data interface, configuration registers, and host control registers, configured to receive simultaneous requests from one or more host processors from amongst the plurality of host processors for the USB device. The USB virtualization unit also includes a pre-fetch direct memory access (DMA) configured to pre-fetch DMA descriptors associated with the requests to store in a buffer. The USB virtualization unit further includes an endpoint specific switching decision logic (ESL) configured to schedule data access based on the DMA descriptors from the host processor's local memory corresponding to each request.

Abstract: Improved current sensing methods and apparatus and conductor apparatus are presented for sensing current in a bus bar or other conductor using one or more circular magnetic sensors or multiple magnetic sensors disposed on a substrate in a pattern surrounding a longitudinal path within the outer periphery of the conductor to avoid or mitigate sensed magnetic field crosstalk and to facilitate use of high sensitivity magnetic sensors at locations inside the conductor periphery in which the magnetic field is relatively small.

Abstract: The present subject matter discloses methods and systems of sharing of peripheral devices in multi host computing systems (100). In one implementation, the method of sharing a peripheral device (116) amongst a plurality of hosts of the multi-host computing system (100) comprises receiving a request to switch the peripheral device (116) from a first operating system running on a first host from amongst the plurality of hosts to a second operating system running on a second host from amongst the plurality of hosts; generating a request for the first operating system to relinquish control of the peripheral device (116); determining the status of the relinquishment based on response generated by the first operating system; initiating a request for the second operating system to install a device driver for the peripheral device (116) upon determining successful relinquishment; and transferring ownership of the peripheral device (116) to the second operating system.

Abstract: Described herein is a multi-host computing system (100) having multiple host processors running different operating systems. In one implementation, a method of playing audio streams received from a plurality of hosts of a multi-host computing system (100), the method comprising receiving a second audio stream from a second host, and changing audio stream parameters associated with the second audio stream from second host to match the corresponding parameter values associated with a first audio stream received from a first host to generate an updated second audio stream. The method further comprises mixing the updated second audio stream with the first audio stream to generate a combined audio stream, and playing the combined audio stream using at least one audio codec (104) of the multi-host computing system (100).

Abstract: Described herein are methods and system for sharing a wireless interface (102) among various multiple host processors in a multi-processor computing system (100) to provide simultaneous access of a wireless network to the host processors.

Abstract: Described herein are methods and system for virtualization of the secure digital (SD) host controller to enable sharing a SD device among various multiple host processors in a multi-processor computing system. In one implementation the method of sharing a SD device amongst a plurality of hosts of a multi-host computing system comprises detecting the SD device on occurrence of a reset event, receiving an enumeration request, from at least a first host and a second host of the plurality of hosts, to enumerate the SD device with respect to the second host, enumerating the SD device with respect to the second host, and initiating data exchange between the SD device and each of the plurality of hosts.

Abstract: Described herein are methods and systems for virtualization of a USB device to enable sharing of the USB device among a plurality of host processors in a multi-processor computing system. A USB virtualization unit for sharing of the USB device include a per-host register unit, each corresponding to a host processor includes one or more of a host register interface, host data interface, configuration registers, and host control registers, configured to receive simultaneous requests from one or more host processors from amongst the plurality of host processors for the USB device. The USB virtualization unit also includes a pre-fetch direct memory access (DMA) configured to pre-fetch DMA descriptors associated with the requests to store in a buffer. The USB virtualization unit further includes an endpoint specific switching decision logic (ESL) configured to schedule data access based on the DMA descriptors from the host processor's local memory corresponding to each request.

Abstract: File system sharing in multi-host computing system (100) running multiple operating systems is described herein. A file systems stored on different data partitions (110-1) and (110-1), of different operating systems (106-1) and (106-2), running on a multi-host computing system (100) may be shared based on file server-client architecture. According to the implementation, an operating system (106-1) may share its file system as file server and other operating system (106-2) may access the shared file system as file client. In one implementation, the sharing of data between multiple hosts is enabled by a dedicated high speed, low latency. inter processor communication bus, FiRE (124).

Abstract: Described herein is a system having a multi-host low pin count (LPC) controller (100) configured to facilitate sharing of common peripheral devices by multiple hosts (115) of a multi-host computing system (110). In one implementation, the multi-host LPC controller (100) interfaces with the hosts (115) via an ON-chip bus or an LPC-IN-chip bus. Further, the multi-host LPC controller (100) includes a LPC-IN controller (160) and a microcontroller (155) to moderate among requests generated by the hosts (115). The requests can be target accesses, DMA accesses, and BM accesses. Also, the multi-host LPC controller (100) is configured to operate in a software mode and an auto mode. Based on the mode the multi-host LPC controller (100) is operating in, the requests generated by the various hosts are moderated.

Abstract: Described herein is a system having a multi-host SATA controller (102) configured to provide communication and control between two or more independent host processors (104) and a single SATA device (108). In one implementation, the multi-host SATA controller (102) includes the device switching layer (206), the device control layer (208), the link layer (210), and the physical layer (212). The device switching layer (206) allows the host processors (104) to issue commands concurrently rather than in sequential order. For this, the device switching layer (206) has independent set of host device registers (214) corresponding to each of the host processors (104). The device switching layer (206) also has independent DMA engines (216) to perform a command pre-fetching from respective host system memories (105). Further, a command switch engine (220) may arbitrate commands in case both the host processors (104) wish to access the SATA device (108) simultaneously.