Abstract: A memory extension memory module, a memory module system, and a memory module is disclosed. The memory module including at least one memory device and a connector for connecting the memory module to a computer system, wherein the memory module additionally includes a surface-mounted connector for connecting a memory extension memory module to the memory module. Furthermore, a method for manufacturing a memory module is disclosed. The memory module including at least one memory device and at least one connector for connecting a memory extension memory module to the memory module, wherein the at least one memory device and the at least one connector are connected to the memory module in a single manufacturing process.

Abstract: A stacked semiconductor memory device includes memory device contacts to externally connect the stacked semiconductor memory device to a printed circuit board. In a dual or quad stack configuration, the stacked semiconductor memory device includes a first package which is stacked above a second package. The first and second packages are preferably designed as FBGA packages, each of them including package contacts. By providing first and second flexible circuit structures to connect the package contacts of the first and second packages to the memory device contacts, a symmetrical stacked package configuration is obtained. This configuration facilitates transmission of signals with improved signal integrity via a bus of the printed circuit board between the stacked semiconductor memory device and a controller chip, even if the frequency of the bus or the load of the stacked semiconductor memory is increased.

Abstract: A chip stack employing BGA or FBGA integrated circuit chip packages is provided. Two chip packages have bottom surfaces attached with sets of electrical contacts, which are oriented towards each other and are electrically connected to conductive patterns formed within the same flex substrate. One set contacts a conductive pattern on a top surface, the other set contacts a pattern on a bottom surface of the flex substrate within a same end portion. The other end portion has a conductive pattern, and is connected to a third set of electrical contacts. The flex substrate is wrapped around an edge of the chip package to connect the third set with the other two sets. Thereby, four chip packages are provided with this design, the layout of conductive traces formed within at least one of the flex substrates is meandered to compensate for length differences with respect to the other flex substrate.

Abstract: A semiconductor memory module has a module board on both sides of which semiconductor memory components are arranged and on an upper face of which a control component is arranged. The control component is connected to the semiconductor memory components via a module bus and bus spurs. The bus is a command address bus using fly-by topology. A semiconductor memory component is connected to the control component via a bus spur that is connected from a junction point to the two symmetrically arranged semiconductor memory components. An additional resistor between line sections of the bus spur reduces fluctuations of address signal levels on the CA bus and thus improves the signal integrity.

Abstract: The invention refers to a buffer chip for driving external input signals applied to a multi-rank dual inline memory module (DIMM) to a predetermined number (N) of memory chips mounted on a printed circuit board of said dual inline memory module, wherein the buffer chip comprises stacked register dies each having several signal drivers, wherein at least two signal drivers are connected in parallel to drive an external input signal to said memory chips.

Abstract: The invention refers to a Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (DIMM) having a predetermined number of DRAM memory chips mounted on a printer circuit board (PCB), wherein each DRAM memory chip comprises a predetermined number of stacked DRAM memory dies which are selectable by a memory rank selection signal (r), wherein the memory rank decoder generates the memory rank selection signal (r) in response to external selection signals applied to the dual inline module (DIMM).

Abstract: The invention refers to a DRAM Memory Chip for a Dual In Line Memory Module (DIMM) having (a) a predetermined number (M) of stacked DRAM memory dies; (b) wherein each DRAM memory die is selectable by a corresponding memory rank signal (r); (c) wherein each DRAM memory die comprises an array of memory cells; (d) wherein a common internal address bus consisting of address lines is provided for addressing the memory cells and is connected to all M stacked DRAM memory dies; (e) wherein M internal data buses consisting of internal data lines are provided for writing data into the memory cells and reading data out of the memory cells of the stacked DRAM memory dies; wherein (f) an integrated redriving unit is provided which comprises: (f1) buffers for all internal address lines provided for driving external address signals applied to address pads of said DRAM memory chip and; (f2) a multiplexer/demultiplexer which switches the internal data lines of the selected DRAM memory die to data pads of said DRAM memory chip

Abstract: The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.

Abstract: A system for simultaneous bi-directional transmission of signals over transmission lines between devices having interface ports includes a first circuit for generating the output signal and a second circuit having first and second terminals. The first terminal is coupled to the first circuit and the second terminal is coupled to the interface port. A signal level at the first terminal corresponds to a first combination of the input and output signals, and a signal level at the second terminal corresponds to a second combination of the input and output signals. A third circuit is coupled to the first and second terminals of the second circuit for determining the input signal based on the first and second combinations of the input and output signal levels.

Abstract: A circuit module has a circuit board, multiple circuit units on the circuit board and at least one clock input on the circuit board for receiving an external clock signal. The circuit module has a first PLL unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a first one of the circuit units. In addition, the circuit module has a second PLL unit on the circuit board for providing an internal clock signal based on the external clock signal to at least a second one of the circuit units.

Abstract: A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A first sub-bus is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same. A second sub-bus is also connected to the main bus and branches into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number. Further, the second sub-bus branches into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.

Abstract: A system for simultaneous bi-directional transmission of signals over transmission lines between devices having interface ports includes a first circuit for generating the output signal and a second circuit having first and second terminals. The first terminal is coupled to the first circuit and the second terminal is coupled to the interface port. A signal level at the first terminal corresponds to a first combination of the input and output signals, and a signal level at the second terminal corresponds to a second combination of the input and output signals. A third circuit is coupled to the first and second terminals of the second circuit for determining the input signal based on the first and second combinations of the input and output signal levels.