Patents by Inventor Sridhar Ramaswamy
Sridhar Ramaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080040221Abstract: An advertisement can be presented by associating a label with an advertisement, receiving input from a user, wherein the input comprises one or more labels, identifying a match between the label associated with the advertisement and the input, and presenting the advertisement to the user. A bid further can be received for presenting the advertisement in response to input from a user that includes the associated label and an advertisement presentation order can be determined based on one or more of the bid, a click-through rate of the advertisement, and a conversion rate of the advertisement. Additionally, a negative label can be associated with the advertisement. Further, an additional input comprising one or more labels can be received from the user, a match can be identified between the negative label and the received additional input, and it can be determined not to present the advertisement based on the identified match.Type: ApplicationFiled: August 8, 2007Publication date: February 14, 2008Applicant: Google Inc.Inventors: Leora Wiseman, Shivakumar Venkataraman, Sridhar Ramaswamy
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Patent number: 7277828Abstract: A method, and associated storage medium containing software and a system, includes extracting a time domain impulse response from parameters that characterize a communication channel, generating a probability distribution function (PDF) of an output voltage based on the impulse response; and computing a relationship between bit error rate and voltage margin based on the final probability distribution function. Generating the PDF of the output voltage may comprise one or more of the following acts: quantizing the impulse response into a plurality of quantized levels, assigning taps to the quantized levels and determining a number of taps assigned to each quantized level, determining allowable voltage levels for each quantized level, and determining a probability of occurrence of each allowable voltage level, determining a PDF for each voltage level; and convolving all of the PDFs for the various voltage levels to obtain the PDF of the output voltage.Type: GrantFiled: February 12, 2004Date of Patent: October 2, 2007Assignee: Texas Instruments IncorporatedInventors: Sridhar Ramaswamy, Song Wu, Bhavesh G. Bhakta
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Patent number: 7269754Abstract: A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.Type: GrantFiled: December 30, 2002Date of Patent: September 11, 2007Assignee: Intel CorporationInventors: Sridhar Ramaswamy, Amit Bodas, Zohar B. Bogin, David E. Freker, Suryaprasad R. Kareenahalli
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Patent number: 7173498Abstract: Disclosed are integrated circuits having multiple electromagnetically emissive devices, such as LC oscillators. The devices are formed on an integrated circuit substrate and are given different planar orientations from each other. Particular integrated circuit packages disclosed are “flip-chip” packages, in which solder bumps are provided on the integrated circuit substrate for flipping and mounting of the finished integrated circuit upon a printed circuit board or other substrate. The solder bumps provide conductive connections between the integrated circuit and the substrate. The orientations and positioning of the emissive devices are such that one or more of the solder bumps are interposed between neighboring emissive devices to act as an electromagnetic shield between them.Type: GrantFiled: September 28, 2004Date of Patent: February 6, 2007Assignee: Texas Instruments IncorporatedInventors: Sridhar Ramaswamy, Hassan O. Ali, Song Wu
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Publication number: 20070005421Abstract: Offers, such as bids in an advertising network, may be determined and/or managed by accepting an ad budget and at least one ad serving constraint, and then generating offer information using the ad budget and the serving constraint(s). The offer may be generated by obtaining, for each of the ad serving constraint(s), a plurality of points, wherein each point includes a cost per event value and an event quantity value. These points collectively define a landscape. A convex landscape for each of the ad serving constraint(s) is then determined from the landscape(s). One or more points from at least one of the convex landscapes is then used to generate the offer information.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Inventors: Wilburt Labio, Sridhar Ramaswamy, Mark Rose
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Patent number: 7105293Abstract: Sets of genetic markers for specific tumor classes are described, as well as methods of identifying a biological sample based on these markers. Also described are diagnostic, prognostic, and therapeutic screening uses for these markers, as well as oligonucleotide arrays comprising these markers.Type: GrantFiled: September 19, 2001Date of Patent: September 12, 2006Assignees: Whitehead Institute for Biomedical Research, Dana-Farber Cancer Institute, Inc.Inventors: Sridhar Ramaswamy, Todd R. Golub, Pablo Tamayo, Michael Angelo
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Publication number: 20060190888Abstract: A system and method is disclosed for computer-assisted transistor design. A new transistor design can be generated based on characteristics of an existing transistor. The system for transistor design receives a first set of parameters for an existing transistor design that are functions of a first geometry that is descriptive of the existing transistor design. Next, the system establishes a set of constraints for the new transistor to be designed. The system then calculates pertinent dimensions of a geometry for the new transistor design based on the constraints and the first set of parameters.Type: ApplicationFiled: January 31, 2005Publication date: August 24, 2006Inventors: Bharadwaj Parthasarathy, Sridhar Ramaswamy, Paul Landman
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Patent number: 7047384Abstract: A method and apparatus for using different timings to latch signals sent by two memory devices of identical design to compensate for differences in the lengths of conductors across which the signals must propagate.Type: GrantFiled: June 27, 2002Date of Patent: May 16, 2006Assignee: Intel CorporationInventors: Amit Bodas, Zohar B. Bogin, David E. Freker, Suryaprasad Kareenahalli, Sridhar Ramaswamy
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Publication number: 20060071714Abstract: Disclosed are integrated circuits having multiple electromagnetically emissive devices, such as LC oscillators. The devices are formed on an integrated circuit substrate and are given different planar orientations from each other. Particular integrated circuit packages disclosed are “flip-chip” packages, in which solder bumps are provided on the integrated circuit substrate for flipping and mounting of the finished integrated circuit upon a printed circuit board or other substrate. The solder bumps provide conductive connections between the integrated circuit and the substrate. The orientations and positioning of the emissive devices are such that one or more of the solder bumps are interposed between neighboring emissive devices to act as an electromagnetic shield between them.Type: ApplicationFiled: September 28, 2004Publication date: April 6, 2006Inventors: Sridhar Ramaswamy, Hassan Ali, Song Wu
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Patent number: 6933567Abstract: An electrostatic discharge (ESD) protection device formed in the semiconductor layer of a semiconductor-on-insulator device, wherein the semiconductor layer has first and second wells. A discharge circuit is formed in the first well, operable to discharge the ESD pulse to ground. A pump circuit is formed in the second well, operable to use a portion of an ESD pulse's voltage to pump current into the first well for allowing the discharge circuit to turn on uniformly. The discharge circuit has a plurality of body nodes to the first well. The pump circuit comprises an input pad for receiving a portion of the ESD pulse's voltage; an MOS transistor having source, gate and drain; a capacitor connected between the input pad and the gate, whereby a rising input voltage pulls the gate transiently high for pumping current into the first well; the source is connected to the body nodes of the discharge circuit, and the drain connected to the input pad.Type: GrantFiled: May 15, 2002Date of Patent: August 23, 2005Assignee: Texas Instruments IncorporatedInventors: Charvaka Duvvury, Sridhar Ramaswamy
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Publication number: 20050182807Abstract: A method, and associated storage medium containing software and a system, comprises extracting a time domain impulse response from parameters that characterize a communication channel, generating a probability distribution function (PDF) of an output voltage based on the impulse response; and computing a relationship between bit error rate and voltage margin based on the final probability distribution function. Generating the PDF of the output voltage may comprise one or more of the following acts: quantizing the impulse response into a plurality of quantized levels, assigning taps to the quantized levels and determining a number of taps assigned to each quantized level, determining allowable voltage levels for each quantized level, and determining a probability of occurrence of each allowable voltage level, determining a PDF for each voltage level; and convolving all of the PDFs for the various voltage levels to obtain the PDF of the output voltage.Type: ApplicationFiled: February 12, 2004Publication date: August 18, 2005Applicant: Texas Instruments IncorporatedInventors: Sridhar Ramaswamy, Song Wu, Bhavesh Bhakta
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Publication number: 20050180498Abstract: An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.Type: ApplicationFiled: February 12, 2004Publication date: August 18, 2005Applicant: Texas Instruments IncorporatedInventors: Bhavesh Bhakta, Sridhar Ramaswamy, Robert Payne, Song Wu
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Publication number: 20050182805Abstract: A filter comprises a tap multiplication circuit and a tap digital-to-analog (“DAC”) unit coupled to the tap multiplication circuit. Further, a plurality of clocks are provided that control timing associated with the tap multiplication circuit and that, permit one tap multiplication to be output while another tap multiplication is being computed for a 1/N rate implementation.Type: ApplicationFiled: February 12, 2004Publication date: August 18, 2005Applicant: Texas Instruments IncorporatedInventors: Bhavesh Bhakta, Sridhar Ramaswamy, Robert Payne, Song Wu
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Publication number: 20050162193Abstract: A sense amplifier and associated method comprise a regenerative latch, an input differential pair of transistors coupled to the regenerative latch, and a leakage device coupled to each of the transistors comprising the input differential pair of transistors. The leakage device is adapted to maintain the input differential pair of transistors in an on state during a pre-charge phase. In other embodiments, the sense amplifier includes a clocked buffer coupled to the outputs of the regenerative latch. The clocked buffer provides additional drive current for the sense amplifier and is clocked by a clock signal that controls the regenerative latch. In yet other embodiments, the sense amplifier includes a secondary hold latch coupled to the outputs of the regenerative latch to maintain an output decision for the sense amplifier while other portions of the sense amplifier pre-charge.Type: ApplicationFiled: January 27, 2004Publication date: July 28, 2005Applicant: Texas Instruments IncorporatedInventors: Robert Payne, Bhavesh Bhakta, Sridhar Ramaswamy, Song Wu
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Patent number: 6912524Abstract: A method for generating an approximate answer to a query in a database environment in which the database has a plurality of base relations. A query relating to a database is received, and an approximate answer to the query is generated such that the approximate answer is based on at least one join synopsis formed from the database. The method further includes steps of forming a sample-tuple set for at least one selected base relation of a plurality of base relations of a database such that each sample-tuple set contains at least one sample tuple from a corresponding base relation, and forming a join synopsis set for each selected base relation such that each join synopsis set contains a join synopsis for each sample tuple in a sample-tuple set. A join synopsis of a sample tuple is based on a join of the sample tuple and at least one descendent relation of the sample tuple. All join synopsis sets form a statistical summary of the database and are stored.Type: GrantFiled: August 12, 2002Date of Patent: June 28, 2005Assignee: Lucent Technologies, Inc.Inventors: Swarup Acharya, Phillip B. Gibbons, Viswanath Poosala, Sridhar Ramaswamy
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Patent number: 6895344Abstract: Determining a substrate resistance network includes receiving a description of a substrate network including nodes. Elements of the substrate network are identified and associated with one or more nodes, where the elements include nwell structures. For each nwell structure, a ring geometry and area geometries result from dividing the nwell structure, where the area geometries represent an inward portion of the nwell structure and where each area geometry is associated with an area resistive element and an area coordinate. The ring geometry represents a perimeter portion of the nwell structure. Side geometries are formed from the ring geometry, each side geometry associated with a side resistive element. An nwell group is formed including the area geometries associated with the nwell structure in accordance with the area coordinates. An nwell resistance network is determined for each nwell group using the area resistive elements and the side resistive elements.Type: GrantFiled: March 25, 2003Date of Patent: May 17, 2005Assignee: Texas Instruments IncorporatedInventor: Sridhar Ramaswamy
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Publication number: 20050050097Abstract: The usefulness, and consequently the performance, of advertisements are improved by allowing businesses to better target their ads to a responsive audience. Location information, such as country, region, metro area, city or town, postal zip code, telephone area code, etc. is determined (or simply accepted) and used. For example, location information may be used in a relevancy determination of an ad. As another example, location information may be used in an attribute (e.g., position) arbitration. Such location information may be associated with price information, such as a maximum price bid. Such location information may be associated with ad performance information. Ad performance information may be tracked on the basis of location information. The content of an ad creative, and/or of a landing page may be selected and/or modified using location information.Type: ApplicationFiled: September 3, 2003Publication date: March 3, 2005Inventors: Leslie Yeh, Sridhar Ramaswamy, Zhe Qian
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Publication number: 20050050027Abstract: The usefulness, and consequently the performance, of advertisements are improved by allowing businesses to better target their ads to a responsive audience. Location information is determined (or simply accepted) and used. For example, location information may be used in a relevancy determination of an ad. As another example, location information may be used in an attribute (e.g., position) arbitration. Such location information may be associated with price information, such as a maximum price bid. Such location information may be associated with ad performance information. Ad performance information may be tracked on the basis of location information. The content of an ad creative, and/or of a landing page may be selected and/or modified using location information. Finally, tools, such as user interfaces, may be provided to allow a business to enter and/or modify location information, such as location information used for targeting and location-dependent price information.Type: ApplicationFiled: April 12, 2004Publication date: March 3, 2005Inventors: Leslie Yeh, Sridhar Ramaswamy, Zhe Qian, Mark Rose
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Publication number: 20040204876Abstract: Determining a substrate resistance network includes receiving a description of a substrate network including nodes. Elements of the substrate network are identified and associated with one or more nodes, where the elements include nwell structures. For each nwell structure, a ring geometry and area geometries result from dividing the nwell structure, where the area geometries represent an inward portion of the nwell structure and where each area geometry is associated with an area resistive element and an area coordinate. The ring geometry represents a perimeter portion of the nwell structure. Side geometries are formed from the ring geometry, each side geometry associated with a side resistive element. An nwell group is formed including the area geometries associated with the nwell structure in accordance with the area coordinates. An nwell resistance network is determined for each nwell group using the area resistive elements and the side resistive elements.Type: ApplicationFiled: March 25, 2003Publication date: October 14, 2004Applicant: Texas Instruments IncorporatedInventor: Sridhar Ramaswamy
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Publication number: 20040128580Abstract: A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.Type: ApplicationFiled: December 30, 2002Publication date: July 1, 2004Inventors: Sridhar Ramaswamy, Amit Bodas, Zohar B. Bogin, David E. Freker, Suryaprasad R. Kareenahalli