Abstract: Various embodiments of systems and methods for maintaining data integrity during data migration are described herein. The systems and methods describe a data migration application that may be installed and executed on a computer device. The data migration application may be connected with multiple data systems via computer network. An authorized user may access the data migration application to migrate data between data systems such as from data source systems to destination systems. In case there is loss of data due to data system interruption, e.g. if a server is abruptly stopped, or software upgrade occurs, the data migration application may create backup data of the failed data migration. The data migration application may reinitiate the data migration to restore the data into the destination system.

Abstract: Various embodiments of systems and methods for maintaining data integrity during data migration are described herein. The systems and methods describe a data migration application that may be installed and executed on a computer device. The data migration application may be connected with multiple data systems via computer network. An authorized user may access the data migration application to migrate data between data systems such as from data source systems to destination systems. In case there is loss of data due to data system interruption, e.g. if a server is abruptly stopped, or software upgrade occurs, the data migration application may create backup data of the failed data migration. The data migration application may reinitiate the data migration to restore the data into the destination system.

Abstract: A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

Abstract: A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

Abstract: A semiconductor device is provided that includes a first pair of P channel field effect transistors (PFET) with a common source connected to a voltage contact and a gate connected to a drain of the other PFET and a pair of N channel field effect transistors (NFET) sized smaller than the first pair of PFETs with a drain connected to the drain of the respective PFET of the first pair of PFETs, a common source connected to a ground contact, and a gate connected to the drain of an opposite PFET of the first pair of PFETs. Additionally, a second pair of PFETs sized larger than the NFETs and approximately one-half that of the first pair of PFETS, each of the second pair of PFETs having a drain respectively coupled to a connection linking the respective drain of the NFET of the pair of NFETs to the drain of the PFET of the first pair of PFETs. Complementary bit lines are included, each of the complementary bit lines respectively connected to a source of the second pair of PFETs.

Abstract: A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

Abstract: A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

Abstract: A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

Abstract: A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

Abstract: A method of manufacturing an integrated circuit (IC) can utilize a shallow trench isolation (STI) technique. The shallow trench isolation technique can be used in an IC process. Separate liners for the trench are used for NMOS and PMOS regions. The liners can induce strain in the substrate.

Abstract: The silicon-on-insulator (SOI) arrangement provides dual SOI film thicknesses for body-resistance control and provides a bulk silicon substrate on which a buried oxide (BOX) layer is provided. The BOX layer has recesses formed therein and unrecessed portions. The silicon layer is formed on the BOX layer and closes the recesses and covers the unrecessed portions of the BOX layer. Shallow trench isolation regions define and isolate first silicon regions from second silicon regions that each include one of the recesses. Floating-body devices are formed within the first silicon regions, which exhibit a first thickness, and body-tied devices are formed within the second silicon regions that include the thicker silicon of the recesses.

Abstract: A structure, for testing relative to an MOS transistor, closely resembles the MOS transistor of interest. For example, certain dimensions and a number of dopant concentrations typically are substantially the same in the test structure as found in corresponding elements of the MOS transistor of interest. However, the regions of the test structure corresponding to the source and drain of the transistor have no halos or extensions that might cause gate overlap; and in the test structure, these regions are of a semiconductor type opposite the type found in the source and drain of the transistor. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for direct electrical measurement of gate length.

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The buried insulation layer includes an oxide trap region disposed along an upper surface of the buried insulation layer, the oxide trap region having a plurality of oxide traps to promote carrier recombination.

Abstract: A structure for testing relative to an MOS transistor, can be easily constructed as part of the CMOS process flow. A doped device well is formed, for example, in a silicon-on-insulator structure. The concentration level in the well corresponds to that for a well of the transistor. Gate insulator and polysilicon layers are formed, and the polysilicon is implanted with dopant, to a concentration level expected in the transistor gate. After gate patterning, the methodology involves forming sidewall spacers and implanting dopant into the active device well, to form regions in the test structure corresponding to the transistor source and drain. Although the concentrations mimic those in the transistor source and drain, these test structure regions are doped with opposite type dopant material. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for measurement of gate length.

Abstract: A method of manufacturing a semiconductor device includes forming a gate, source/drain extensions, buffer regions, and source/drain regions. The gate is formed over a semiconductor layer, and the source/drain extensions are formed within the semiconductor layer and adjacent the gate. The buffer regions are formed within first amorphous implant regions, and the source/drain regions are formed within second amorphous implant regions. The buffer regions and the source/drain regions are activated using solid-phase epitaxy whereby sidewalls of the activated buffer regions and the activated source/drain regions are substantially vertical.

Abstract: A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.

Abstract: A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.

Abstract: An SOI semiconductor and method for making the same includes a substrate and dielectric support structures that support a silicon body above the substrate. This creates a void underneath the silicon body and thereby reduces the capacitance between the source/drain regions on body and the substrate.

Abstract: A method of making a Silicon-on-Insulator (SOI) transistor includes forming a body layer that is fully depleted when the SOI transistor is in a conductive state and forming first p+ regions adjacent each of the SOI transistor source/drain regions to adjust the SOI transistor threshold voltage. To suppress punch-through current, an additional implant step is carried out to form second p+ regions adjacent first implant regions.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.