Patents by Inventor Srinath Krishnan
Srinath Krishnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6441433Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a multi-thickness silicide layer formed on the main source and drain regions and source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the silicide layer which is formed on the main source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate.Type: GrantFiled: April 2, 2001Date of Patent: August 27, 2002Assignee: Advanced Micro Devices, Inc.Inventors: William G. En, Srinath Krishnan, Dong-Hyuk Ju, Bin Yu
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Patent number: 6429083Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which has been treated subsequent to its deposition, e.g., by ion implantation, to augment its etch rate with a room temperature etchant, e.g., dilute aqueous HF. The treated spacers are removed with the dilute, aqueous HF after implantation of moderately or heavily-doped source/drain regions but prior to any post-implantation annealing processing, in order not to increase the etch resistance of the spacer material by thermally-induced densification.Type: GrantFiled: June 21, 2000Date of Patent: August 6, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Emi Ishida, Srinath Krishnan, Ming Hao, Effiong Ibok
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Patent number: 6429054Abstract: A method of forming a semiconductor-on-insulator (SOI) device. The method includes providing an SOI wafer having an active layer, a substrate and a buried insulator layer therebetween; defining an active region in the active layer; forming a source, a drain and body in the active region, the source and the drain forming respective hyperabrupt junctions with the body, the hyperabrupt junctions being formed by an SPE process which includes amorphizing the at least one of the source and the drain, implanting dopant ion species and recrystalizing at temperature of less than 700° C.; forming a gate disposed on the body such that the source, drain, body and gate are operatively arranged to form a transistor; and forming a silicide region in each of the source and the drain, the silicide regions being spaced from the respective hyperabrupt junctions by a lateral distance of less than about 100 Å.Type: GrantFiled: June 11, 2001Date of Patent: August 6, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Srinath Krishnan, Witold P. Maszara
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Patent number: 6420767Abstract: A transistor structure is provided comprising a source region having a N+ source region and a N− lightly doped source region. The structure also comprises a drain region having a N+ drain region and a N− lightly doped drain region. A P++ heavily doped region is provided. The P++ region resides alongside at least a portion of at least one of the N− lightly doped source region and N− lightly doped drain region. A P+ body region resides below a gate of the device and between the source and drain regions. The P+⇄ heavily doped region provides a capacitive coupling between a body region and the gate of the device and form a capacitive voltage divider with the junction capacitance of the device.Type: GrantFiled: June 28, 2000Date of Patent: July 16, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Srinath Krishnan, John C. Holst, Bin Yu
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Patent number: 6407428Abstract: A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. The channel region of the FET includes a buried and confined metal plate for controlling short channel effects without significantly increasing junction capacitance.Type: GrantFiled: June 15, 2001Date of Patent: June 18, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Srinath Krishnan, Judy Xilin An
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Patent number: 6399452Abstract: A low thermal budget transistor is fabricated by first forming a gate on a semiconductor substrate. First amorphous regions and first inactive dopant regions are then created in the substrate by ion implantation. Sidewall spacers, which align subsequent implantation steps, are formed adjacent to the gate. Thereafter, second amorphous regions and second inactive dopant regions are created in the substrate by ion implantation. Dopants in the first and second inactive dopant regions are then activated using a low temperature annealing process to create source/drain regions and source/drain extension regions. The aforementioned process simplifies the fabrication of a low thermal budget transistor by dispensing with the requirement to remove the sidewall spacers.Type: GrantFiled: July 8, 2000Date of Patent: June 4, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Srinath Krishnan, Witold Maszara
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Patent number: 6362063Abstract: A shallow abrupt junction is formed in a single crystal substrate, for example, to form a pn junction in a diode or a source drain extension in a transistor. An amorphous layer is formed at the surface of the substrate by implanting an electrically inactive ion, such as germanium or silicon, into the substrate. The amorphous/crystalline interface between the amorphous layer and the base crystal substrate is located at the depth of the desired junction. A dopant species, such as boron, phosphorus or arsenic is implanted into the substrate so that peak concentration of the dopant is at least partially within the amorphous layer. The amorphous layer can be formed either before or after the implanting of the dopant species. A low temperature anneal is used to recrystallize the amorphous layer through solid phase epitaxy, which also activates the dopant within the amorphous layer. The dopant located beneath the original amorphous/crystalline interface remains inactive.Type: GrantFiled: January 6, 1999Date of Patent: March 26, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Witold P. Maszara, Srinath Krishnan, Shekhar Pramanick
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Patent number: 6359298Abstract: A MOSFET multiple device structure is provided. The structure comprises a plurality of MOSFET devices sharing at least one heavily doped region extending underneath a gate region of at least two of the plurality of MOSFET devices. The shared heavily doped region provides a capacitive coupling forming a capacitive voltage divider with the junction capacitance of the MOSFET devices between a body region and the gate region.Type: GrantFiled: July 20, 2000Date of Patent: March 19, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Srinath Krishnan
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Patent number: 6342423Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated by a process employing removable sidewall spacers made of a material, such as UV-nitride, which is readily etched in its as-deposited, undensified state but difficult-to-etch in its thermally annealed, densified state. The as-deposited, undensified spacers are removed by etching with dilute aqueous HF after implantation of heavily-sloped source/drain junction regions but prior to annealing of the implant for dopant diffusion/activation and lattice damage relaxation. Lightly-or moderately doped, shallow-depth source/drain extensions are implanted and annealed after spacer removal.Type: GrantFiled: September 22, 2000Date of Patent: January 29, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Emi Ishida, Srinath Krishnan, Ming Yin Hao, Effiong Ibok
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Patent number: 6326247Abstract: A method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. A semiconductive layer is provided having an oxide layer thereon. At least one trench is then etched into the oxide layer. The oxide layer is then filled with a substrate material layer and then ground and polished down to form a generally planar upper surface. The trench filled regions of the oxide layer form an oxide layer having regions of a first thickness and the remaining regions of the oxide layer are of a second thickness. The semiconductor wafer can then be flipped and partially depleted transistor devices formed over the regions of the first thickness and fully depleted transistor devices formed over regions of the second thickness.Type: GrantFiled: June 28, 2000Date of Patent: December 4, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Srinath Krishnan, Matthew S. Buynoski
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Patent number: 6284608Abstract: A method of manufacturing an accumulation mode n-channel Silicon On Insulator (SOI) transistor includes forming an intrinsic silicon body region implanted with two deep Boron and one shallow Phosphorous implants; forming source/drain regions each implanted with Arsenic; and forming p-type regions adjacent each of the source and drain regions and disposed along the transistor channel. The SOI transistor has a higher transconductance than known SOI devices.Type: GrantFiled: February 1, 2000Date of Patent: September 4, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Zoran Krivakapic, Srinath Krishnan, Witold Maszara
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Patent number: 6274915Abstract: A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode. A method of fabricating an MOS device including a polysilicon gate electrode with increased depletion is also provided.Type: GrantFiled: January 5, 1999Date of Patent: August 14, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Srinath Krishnan, Ming-Yin Hao, David Bang, Witold Maszara
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Patent number: 6238960Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration.Type: GrantFiled: January 14, 2000Date of Patent: May 29, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Witold P. Maszara, Srinath Krishnan, Ming-Ren Lin
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Patent number: 6204138Abstract: A method of forming a MOSFET device is provided. First lightly doped regions are formed, the first lightly doped regions including LDD extension regions of the device. Second very lightly doped regions are formed at least partially below the first lightly doped regions, respectively, the second very lightly doped regions having a dopant concentration less than the first lightly doped regions, and the second very lightly doped regions being implanted at a higher energy level than the first lightly doped regions.Type: GrantFiled: March 2, 1999Date of Patent: March 20, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Srinath Krishnan, Witold P. Maszara, Ming-Ren Lin
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Patent number: 6184112Abstract: In accordance with the present invention, an amorphous layer is formed in a crystalline substrate (e.g., the channel region of a MOSFET transistor) by, for example, implanting ions of an inert specie such as germanium. A dopant is implanted so that it overlaps with the amorphous layer. Subsequently, low temperature recrystallization of the amorphous layer leads to an abrupt retrograded layer of active dopant in the channel region of the MOSFET. This retrograded dopant layer could be formed before or after the formation of the gate electrode.Type: GrantFiled: December 2, 1998Date of Patent: February 6, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Witold P. Maszara, Srinath Krishnan, Shekhar Pramanick
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Patent number: 6100558Abstract: A method for fabricating a MOSFET device is provided. The method includes a step of forming a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be over source/drain extension regions of the device; and the second gate oxide material is formed over a channel region of the device. The first gate oxide material has a low dielectric constant and provides for mitigating gate fringing field effects. The second gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device. Controlled uniform growth of the second gate oxide material is facilitated because of the thickness thereof.Type: GrantFiled: July 16, 1998Date of Patent: August 8, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Zoran Krivokapic, Srinath Krishnan, Geoffrey Choh-Fei Yeap, Matthew Buynoski
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Patent number: 6087208Abstract: A method for fabricating a MOSFET device is provided. The method includes a step of fining a gate oxide including first and second gate oxide materials. The first gate oxide material has a higher dielectric constant than the second gate oxide material. The first gate oxide material is formed to be over source/drain extension regions of the device; and the second gate oxide material is formed over a channel region of the device. The first gate oxide material has a low dielectric constant and provides for mitigating gate fringing field effects. The second gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device. Controlled uniform growth of the second gate oxide material is facilitated because of the thickness thereof.Type: GrantFiled: March 31, 1998Date of Patent: July 11, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Zoran Krivokapic, Srinath Krishnan, Geoffrey Choh-Fei Yeap, Matthew Buynoski
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Patent number: 6060364Abstract: A method (100) of forming a transistor (50, 80) includes forming a gate oxide (120) over a portion of a semiconductor material (56, 122) and forming a doped polysilicon film (124) having a dopant concentration over the gate oxide (122). Subsequently, the doped polysilicon film (124) is etched to form a gate electrode (52) overlying a channel region (58) in the semiconductor material (56, 122), wherein the gate electrode (52) separates the semiconductor material into a first region (60) and a second region (68) having the channel region (58) therebetween. The method (100) further includes forming a drain extension region (64) in the first region (60) and a source extension region (72) in the second region (68), and forming a drain region (62) in the first region (60) and a source region (70) in the second region (68). The source/drain formation is such that the drain and source regions (62, 70) have a dopant concentration which is less than the polysilicon film (124) doping concentration.Type: GrantFiled: March 2, 1999Date of Patent: May 9, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Witold P. Maszara, Srinath Krishnan, Ming-Ren Lin
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Patent number: 5960322Abstract: A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.Type: GrantFiled: December 19, 1997Date of Patent: September 28, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Qi Xiang, Geoffrey Yeap, Srinath Krishnan, Ming-Ren Lin