Abstract: An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.

Abstract: An SOI CMOS inverter circuit in which a silicide layer in combination with body tie regions tie a p-type body region and an n-type body region together. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained. The silicide layer permits excess carriers to be recombined via the respective body regions so that the body region potential does not get modulated by generation/recombination effects. Thus, a hysteresis effect in the inverter circuit will be reduced.

Abstract: In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate, involving the steps of providing a first silicon substrate and a second silicon substrate; surface modifying at least one of the first silicon substrate and the second silicon substrate by forming a pattern thereon; forming a first insulation layer over the first silicon substrate to provide a first structure and a second insulation layer over the second silicon substrate to provide a second structure; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer; and removing a portion of the first or second silicon substrate thereby providing the silicon-on-insulator substrate.

Abstract: A fully depleted silicon on insulator (SOI) field effect transistor (FET) includes a gate positioned above a channel region and an aligned back gate positioned below the channel region and the buried oxide later. Alignment of the back gate with the gate is achieved utilizing a disposable gate process and retrograde doping of the backgate.

Abstract: An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device is formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a backside contact plug adjacent and in thermal contact with at least one of the anode or the cathode, the backside contact plug traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract: A MOSFET formed in semiconductor-on-insulator format. The MOSFET includes a source and a drain formed in a layer of semiconductor material, each having an extension region and a deep doped region. A body is formed between the source and the drain and includes a first damaged region adjacent the extension of the source and a second damaged region adjacent the extension of the drain. The first and second damaged regions include defects caused by amorphization of the layer of semiconductor material. A gate electrode, the source, the drain and the body are operatively arranged to form a transistor.

Abstract: A Silicon-on-Insulator (SOI) transistor includes an intrinsic body layer that is fully depleted when in a conductive state. The transistor includes a shallow pocket of dopants adjacent to each of its source and drain regions. The shallow pockets are of a conductivity type opposite to that of the source and drain regions and raise the threshold voltage of the transistor. The transistor also includes a deep pocket of dopants adjacent each of the source and drain regions to suppress the punch-through current.

Abstract: An integrated test circuit for a silicon on insulator circuit structure is formed on the same wafer as the circuit structure. The wafer includes an input circuit coupled to the silicon on insulator circuit structure which generates a drive signal for operating the silicon on insulator circuit structure and an output circuit which processes a response signal from the circuit structure to generate an output signal representing certain characteristics of the silicon on insulator circuit structure.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a plurality of spacers used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The active layer includes an abrupt region disposed along a lower portion of the active layer, the abrupt region having the same P or N doping type as a doping type of a body region.

Abstract: A semiconductor-on-insulator (SOI) device formed on an SOI structure with a buried oxide (BOX) layer disposed therein and an active region disposed on the BOX layer having active regions defined by isolation trenches and the BOX layer. The SOI device includes a gate formed over one of the active regions. The gate defines a channel interposed between a source and a drain formed within one of the active regions. The SOI device includes a leakage enhanced region within the BOX layer defined by the gate.

Abstract: An SOI CMOS inverter circuit in which a silicide layer in combination with body tie regions tie a p-type body region and an n-type body region together. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained. The silicide layer permits excess carriers to be recombined via the respective body regions so that the body region potential does not get modulated by generation/recombination effects. Thus, a hysteresis effect in the inverter circuit will be reduced.

Abstract: A method of forming a MOSFET device is provided including the steps of forming N− lightly doped source and drain extension regions in the top silicon layer, forming spacers above the N− lightly doped source and drain extension regions and forming N+ source and N+ drain regions in the top silicon layer. A silicide film is then provided over the drain and source regions and the spacers are removed. An ion implantation step is then performed to form damaged sidewall regions in the source body and drain body junction.

Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.

Abstract: A method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. At least one trench is etched into a bulk semiconductor wafer. The wafer is then filled with an insulating material and polished down to the surface level of the semiconductor wafer to form a generally planar surface. A handle wafer is provided having a substrate layer and an insulating layer. The planar surface of the semiconductor wafer is bonded to the insulating layer of the handle wafer. The trench filled regions of the semiconductor wafer form regions of a first thickness and the remaining regions of the semiconductor wafer form regions of a second thickness. Fully depleted transistor device can then be formed in the regions of the first thickness and partially depleted transistor devices can be formed in regions of the second thickness.

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes a semiconductor substrate layer; an insulator layer disposed on the substrate layer; a semiconductor active region disposed on the insulator layer, the active region including a source, a drain, and a body disposed therebetween, at least one of the source and the drain forming a hyperabrupt junction with the body; and a gate disposed on the body such that the gate, source, drain and body are operatively arranged to form a transistor. The at least one of the source and drain forming the hyperabrupt junction with the body includes a silicide region. The silicide region has a generally vertical interface, which is laterally spaced apart from the hyperabrupt junction by about 60 Å to about 150 Å.

Abstract: A charge limiting system is provided that maintains the charge level of a body for a multiple MOSFET device structure. The multiple MOSFET device include a number of bodies linked to one another or a single body, such as a well, being employed for all devices. The single body or bodies are provided with at least one contact that extends to another layer, so that the body can be coupled to the charge limiting system. The charge limiting system includes a charge detector system that monitors the charge level on the body or bodies and a switching system for coupling the body or bodies to a fixed potential, if the charge level of the body or bodies reaches an unacceptable level. The switching system couples the body or bodies to ground for an npn type transistor and to VDD for pnp type transistors.

Abstract: An electrostatic discharge (ESD) protection device for a silicon-on-insulator (SOI) integrated circuit having a silicon substrate with a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer having active regions defined by isolation trenches. The ESD protection device formed on the SOI integrated circuit and has an anode and a cathode formed within one of the active regions and coupled respectively to a first and a second node; and a filled backside contact opening disposed under and in thermal contact with at least one of the anode or the cathode, the backside contact opening traversing the buried oxide layer to thermally couple the one of the active regions and the substrate.

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.