Abstract: An angle of arrival (AoA) of an electromagnetic wave is determined. A phase of an antenna signal associated with each of two receive antenna is measured. A measured phase difference of arrival (PDoA) of the electromagnetic wave is determined based on the measured phase of each of the antenna signals. The measured PDoA is corrected based on one or more crosstalk factors associated with the two receive antennas. The AoA of the electromagnetic wave at the two receive antenna is generated based on the corrected measured PDoA.

Abstract: A moving object detector detects a moving object in a channel. The detection comprises the detector receiving a plurality of frames based on a transmitter transmitting a plurality of frames over a channel. One or more channel impulse responses (CIRs) of the channel is determined based on the received plurality of frames. The detector determines a CIR phase for each of the CIRs and a phase signal is formed based on a phase value of the CIR phase for each of the CIRs. The detector compares the phase signal with a target signal and detects the moving object in the channel based on the comparison.

Abstract: A system for localizing an ultra-wide band (UWB) apparatus comprises a UWB transceiver that identifies and extracts features of at least one channel impulse response (CIR); and a special-purpose processor that applies a machine learning classification process to the extracted CIR features to localize the UWB apparatus in a vehicle.

Abstract: A method for determining phase continuity of a local oscillator signal generated using a frequency divider is provided. The method includes determining at least one sample of the local oscillator signal. Further, the method includes determining information on the phase continuity using the at least one sample.

Abstract: The disclosure relates to determining a carrier phase shift between a first transceiver (101) and a second transceiver (103), each transceiver comprising a local oscillator for generating a carrier signal, an example method for which comprises: the first transceiver (101) generating and transmitting a first continuous wave carrier signal packet (201); the second transceiver (103) receiving the first continuous wave carrier signal packet (201); the second transceiver (103) calculating a first phase correction (PCTB) based on a comparison between the received first continuous wave carrier signal packet (201) and a local oscillator carrier signal at the second transceiver (103); the second transceiver (103) generating and transmitting a second continuous wave carrier signal packet (203); the first transceiver (101) receiving the second continuous wave carrier signal packet (203); the first transceiver (101) calculating a second phase correction (PCTA) based on a comparison between the received second continuous

Abstract: An ultra-wideband (UWB) wireless communication system, comprises a first wireless apparatus; a second wireless apparatus that participates in a first ranging sequence with the first wireless apparatus; and a transmission channel between the first and second wireless apparatuses that transmits data of the first ranging sequence. At least one of the first wireless apparatus or second wireless apparatus generating at least one channel impulse response (CIR) and determining from the at least one CIR whether the transmission channel includes a line-of-sight channel. A special purpose processor reduces a current performance level of at least one of the first and second wireless apparatuses during a second ranging sequence in response to a determination that the transmission channel includes the line-of-sight channel.

Abstract: A method and apparatus for generating a digital signal indicating a time between a start and a stop signal, including a short inverter ring operable to generate a clock signal. The clock signal is provided to a time-interleaved counter array that distributes the clock signal on a plurality of clock outputs as interleaved clock signals. Each interleaved clock signal is provided to a counter that counts a partial count value. The partial count values are combined to obtain a total count value as the digital signal indicating the time. A fine resolution signal is obtained from a chain of stochastic flip flops connected to outputs of the inverters in the short inverter ring. Multiple clock signal outputs of the inverter ring may be provided to multiple interleaved counters.

Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.

Abstract: A method for determining phase continuity of a local oscillator signal generated using a frequency divider is provided. The method includes determining at least one sample of the local oscillator signal. Further, the method includes determining information on the phase continuity using the at least one sample.

Abstract: A receiver for reducing a distortion component within a baseband receive signal is provided. The baseband receive signal is derived from a radio frequency signal. The receiver includes a signal generation unit configured to generate a local oscillator signal. The local oscillator signal comprises a first signal component having a first frequency related to a desired signal component of the radio frequency signal, and a second signal component having a second frequency related to a frequency of an interfering signal. The receiver further includes a mixer coupled to the signal generation unit. The mixer is configured to receive the local oscillator signal, wherein the mixer receives the local oscillator signal with the interfering signal.

Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.

Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.

Abstract: A receiver for reducing a distortion component within a baseband receive signal is provided. The baseband receive signal is derived from a radio frequency signal. The receiver includes a signal generation unit configured to generate a local oscillator signal. The local oscillator signal comprises a first signal component having a first frequency related to a desired signal component of the radio frequency signal, and a second signal component having a second frequency related to a frequency of an interfering signal. The receiver further includes a mixer coupled to the signal generation unit. The mixer is configured to receive the local oscillator signal, wherein the mixer receives the local oscillator signal with the interfering signal.

Abstract: A transceiver includes local oscillator (LO) signal circuitry configured to output an LO signal having an LO frequency and mixer circuitry configured to input the LO signal and an information signal that encodes communication data and output a shifted signal that corresponds to the information signal shifted to a desired frequency. The LO signal circuitry includes selection circuitry and generation circuitry. The selection circuitry is configured to select a pulse pattern and a gap duration based at least on a target harmonic of the LO frequency to be suppressed. The pulse pattern includes at least two pulses spaced apart by a gap having the gap duration. The generation circuitry is configured to generate an LO signal characterized by the selected pulse pattern and gap duration.

Abstract: A user equipment (UE) to compensating for the frequency disturbance. The apparatus may include baseband circuitry and radio frequency (RF) circuitry. The baseband circuitry may detect a request for connectivity circuitry to perform an operation that generates a signal creating a frequency disturbance at the RF circuitry and send operation information indicating a type of the operation to radio frequency (RF) circuitry. The RF circuitry may include a processor and a phase lock loop (PLL) subsystem. The processor may receive the operation information; determine timing information correlating to the operation information; and send the timing information to a phase lock loop (PLL) subsystem indicating the type of the operation and a time of the operation. The PLL subsystem may generate an inverse signal to compensate for the frequency disturbance.

Abstract: Methods and apparatus for calibrating a polar transmitter are provided. Calibration circuitry is configured to generate an adjustment signal that communicates an amplitude modulation/phase modulation (AMPM) delay value to AMPM delay circuitry that is configured to delay, based at least on the AMPM delay value, output of a signal by digital signal processing circuitry (DSP) in the polar transmitter. The calibration circuitry includes signal generation circuitry, estimation circuitry, and delay circuitry. The signal generation circuitry is configured to generate a calibration signal to control the polar transmitter to generate a calibration transmit signal. The estimation circuitry is configured to receive a result signal that is based on the calibration transmit signal and estimate the AMPM delay value based at least on the result signal. The delay circuitry is configured to provide an adjustment signal to communicate the estimated AMPM delay value to the AMPM delay circuitry.

Abstract: A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values.

Abstract: A transceiver includes local oscillator (LO) signal circuitry configured to output an LO signal having an LO frequency and mixer circuitry configured to input the LO signal and an information signal that encodes communication data and output a shifted signal that corresponds to the information signal shifted to a desired frequency. The LO signal circuitry includes selection circuitry and generation circuitry. The selection circuitry is configured to select a pulse pattern and a gap duration based at least on a target harmonic of the LO frequency to be suppressed. The pulse pattern includes at least two pulses spaced apart by a gap having the gap duration. The generation circuitry is configured to generate an LO signal characterized by the selected pulse pattern and gap duration.

Abstract: An apparatus of a mobile device may calibrate RF circuitry for mobile communications. The apparatus may include phase locked loop (PLL) comprising a digital controlled oscillator (DCO) and one or more processors coupled to the PLL. The one or more processors may determine a coarse tuning setting for the DCO based on a target frequency of a wireless channel; and calculate, a DCO gain value for the coarse tuning setting based on a calibration DCO gain value for a calibration coarse tuning setting.

Abstract: This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.