Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.

Abstract: The present disclosure relates to a frequency synthesizer. The frequency synthesizer includes a phase comparator having first and second input nodes. The first input node receives a reference signal having a reference frequency. A channel control block has an input that receives a channel word and an output coupled to the second input node of the phase comparator. A local oscillator (LO) output node provides an LO signal having an LO frequency based on the reference frequency and the channel word. A feedback back couples the LO output node to the second input node of the phase comparator through the channel control block. A non-linear error correction element is operably coupled on a coupling path extending between the phase comparator and the DCO.

Abstract: Some embodiments of the present disclosure relate to a fractional divider for frequency generation. The fractional divider includes a permutation network including a plurality of phase input terminals and a plurality of permuted phase output terminals with a plurality of propagation paths extending therebetween. Multiple propagation paths extend between a phase input terminal and a permuted phase output terminal. A control unit switches an input signal on the phase input terminal through the multiple propagation paths in time to produce a permuted phase signal on the permuted phase output terminal. A phase selection element individually switches the permuted phase output terminals to an output terminal of the fractional divider in time to generate an output signal. The output signal has an output frequency that is a non-unity fraction of an input frequency of the input signal.

Abstract: A circuit includes an oscillator, a variable phase adjuster and a feedback loop. The oscillator is configured to provide an RF signal, wherein the oscillator is configured to operate in a free-running mode of operation. The variable phase adjuster is configured to provide a phase adjusted signal, a phase of which is shifted with respect to a phase of an output signal of the oscillator, or with respect to a phase of a signal derived from the output signal of the oscillator. The feedback loop is configured to provide a control value for controlling the variable phase adjuster based on the phase adjusted signal and a reference oscillator signal to counteract a phase error of the phase adjusted signal.

Abstract: The present disclosure relates to a frequency synthesizer. The frequency synthesizer includes a phase comparator having first and second input nodes. The first input node receives a reference signal having a reference frequency. A channel control block has an input that receives a channel word and an output coupled to the second input node of the phase comparator. A local oscillator (LO) output node provides an LO signal having an LO frequency based on the reference frequency and the channel word. A feedback back couples the LO output node to the second input node of the phase comparator through the channel control block. A non-linear error correction element is operably coupled on a coupling path extending between the phase comparator and the DCO.