Abstract: Pulse generation circuitry includes edge generation circuitry and edge combination circuitry. The edge generation circuitry includes a first digital-to-time converter (DTC) configured to input a first phase signal that includes a first phase edge and a second phase signal that includes a second phase edge. The edge generation circuitry is configured to generate a first pulse edge signal comprising a first pulse edge at a selected location between the first phase edge and the second phase edge. The edge combination circuitry is configured to combine the first pulse edge signal and a second pulse edge signal including a second pulse edge to generate a pulse signal.

Abstract: A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values.

Abstract: A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path, and a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path. Employing a noise shaping circuit according to an example may improve an overall noise performance.

Abstract: A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values.

Abstract: A circuit according to an example includes a digital-to-time converter and a signal processing circuit coupled to the digital-to-time converter and configured to generate a processed signal derived from a signal provided to the signal processing circuit, the processed signal including a predetermined phase relation with respect to the signal provided to the signal processing circuit, wherein the circuit is configured to receive a reference signal and to generate an output signal based on the received reference signal. The a measurement circuit is configured to measure a delay between the output signal and the reference signal, wherein the output of the digital-to-time converter is coupled to a memory configured to store calibration data of the digital-to-time converter based on the measured delay.

Abstract: Predictive time-to-digital converters (TDCs) and methods for providing a digital representation of a time interval are disclosed herein. In an example, a TDC can include a delay line, a selection circuit, and a latch circuit. The delay line can include a plurality of delay elements configured to propagate a first edge of a first signal sequentially through the plurality of delay elements. The selection circuit can be configured to receive the first signal, to receive prediction information, and to route the first signal to an input of one of the plurality of delay elements based on the prediction information. The latch circuit can receive a second signal and can latch a plurality of outputs of the delay line upon reception of a second edge of the second signal. An output of the latch circuit can provide an indication of a delay between the first edge and the second edge.

Abstract: A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique.

Abstract: A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.

Abstract: A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path, and a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path. Employing a noise shaping circuit according to an example may improve an overall noise performance.

Abstract: Predictive time-to-digital converters (TDCs) and methods for providing a digital representation of a time interval are disclosed herein. In an example, a TDC can include a delay line, a selection circuit, and a latch circuit. The delay line can include a plurality of delay elements configured to propagate a first edge of a first signal sequentially through the plurality of delay elements. The selection circuit can be configured to receive the first signal, to receive prediction information, and to route the first signal to an input of one of the plurality of delay elements based on the prediction information. The latch circuit can receive a second signal and can latch a plurality of outputs of the delay line upon reception of a second edge of the second signal. An output of the latch circuit can provide an indication of a delay between the first edge and the second edge.

Abstract: A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.

Abstract: A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique.

Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.

Abstract: This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.

Abstract: A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal processing circuit configured to receive a reference signal and configured to generate a sequence of digital values indicative of a phase relation between the reference signal and the output signal or a signal derived from the output signal, and a digital data processing circuit configured to generate a sequence of processed values at a lower frequency than a frequency of the sequence of the digital values, each processed value being based on a plurality of the digital values of the sequence of digital values, wherein the control signal is based on the sequence of processed values.

Abstract: A circuit according to an example includes a digital-to-time converter and a signal processing circuit coupled to the digital-to-time converter and configured to generate a processed signal derived from a signal provided to the signal processing circuit, the processed signal including a predetermined phase relation with respect to the signal provided to the signal processing circuit, wherein the circuit is configured to receive a reference signal and to generate an output signal based on the received reference signal. The a measurement circuit is configured to measure a delay between the output signal and the reference signal, wherein the output of the digital-to-time converter is coupled to a memory configured to store calibration data of the digital-to-time converter based on the measured delay.

Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.

Abstract: A circuit includes an oscillator, a variable phase adjuster and a feedback loop. The oscillator is configured to provide an RF signal, wherein the oscillator is configured to operate in a free-running mode of operation. The variable phase adjuster is configured to provide a phase adjusted signal, a phase of which is shifted with respect to a phase of an output signal of the oscillator, or with respect to a phase of a signal derived from the output signal of the oscillator. The feedback loop is configured to provide a control value for controlling the variable phase adjuster based on the phase adjusted signal and a reference oscillator signal to counteract a phase error of the phase adjusted signal.

Abstract: Representative implementations of devices and techniques provide bipolar time-to-digital conversion. For example, either a positive time duration or a negative time duration may be converted to a digital representation by a linear time-to-digital converter (TDC). A set of logic functions may be applied to the input of the TDC to provide start and/or stop signals for the TDC. Further, a correction component may be applied to an input or an output of the TDC to compensate for a delay offset of the TDC.

Abstract: Some embodiments of the present disclosure relate to a fractional divider for frequency generation. The fractional divider includes a permutation network including a plurality of phase input terminals and a plurality of permuted phase output terminals with a plurality of propagation paths extending therebetween. Multiple propagation paths extend between a phase input terminal and a permuted phase output terminal. A control unit switches an input signal on the phase input terminal through the multiple propagation paths in time to produce a permuted phase signal on the permuted phase output terminal. A phase selection element individually switches the permuted phase output terminals to an output terminal of the fractional divider in time to generate an output signal. The output signal has an output frequency that is a non-unity fraction of an input frequency of the input signal.