Patents by Inventor Sung Hyun Jo
Sung Hyun Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190027219Abstract: A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch.Type: ApplicationFiled: September 21, 2018Publication date: January 24, 2019Inventors: Hagop Nazarian, Sung Hyun Jo
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Patent number: 10134984Abstract: Providing an electrode for a two-terminal memory device is described herein. By way of example, the electrode can comprise a contact surface that comprises at least one surface discontinuity. For instance, the electrode can have a gap, break, or other discontinuous portion of a surface that makes electrical contact with another component of the two-terminal memory device. In one example, the contact surface can comprise an annulus or an approximation of an annulus, having a discontinuity within a center of the annulus, for instance. In some embodiments, a disclosed electrode can be formed from a conductive layer deposited over a non-continuous surface formed by a via or trench in an insulator, or over a pillar device formed from or on the insulator.Type: GrantFiled: December 31, 2014Date of Patent: November 20, 2018Assignee: CROSSBAR, INC.Inventors: Sung Hyun Jo, Joanna Bettinger, Xianliang Liu, Zeying Ren, Xu Zhao, Fnu Atiquzzaman
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Patent number: 10134985Abstract: Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.Type: GrantFiled: October 19, 2007Date of Patent: November 20, 2018Assignee: The Regents of the University of MichiganInventors: Wei Lu, Sung Hyun Jo
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Patent number: 10134469Abstract: Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.Type: GrantFiled: June 29, 2017Date of Patent: November 20, 2018Assignee: CROSSBAR, INC.Inventors: Lin Shih Liu, Tianhong Yan, Sung Hyun Jo, Sang Nguyen, Hagop Nazarian
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Patent number: 10121540Abstract: Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.Type: GrantFiled: October 30, 2017Date of Patent: November 6, 2018Assignee: CROSSBAR, INC.Inventor: Sung Hyun Jo
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Patent number: 10096362Abstract: A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch.Type: GrantFiled: March 24, 2017Date of Patent: October 9, 2018Assignee: CROSSBAR, INC.Inventors: Hagop Nazarian, Sung Hyun Jo
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Patent number: 10090463Abstract: Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.Type: GrantFiled: August 9, 2013Date of Patent: October 2, 2018Assignee: The Regents of the University of MichiganInventors: Wei Lu, Sung Hyun Jo
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Patent number: 10079060Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.Type: GrantFiled: April 24, 2017Date of Patent: September 18, 2018Assignee: CROSSBAR, INC.Inventors: Sung Hyun Jo, Hagop Nazarian, Lin Shih Liu
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Patent number: 10056280Abstract: A transporting system includes a first rail including a first region and a second region, the first region being a region where the first rail extends linearly and the second region being a region where the first rail is curved. A second rail includes a third region, separated from the first region, and a fourth region overlapping the second region, wherein the first and second rails merge at a joining location that includes the second region and the fourth region. Optical lines are disposed in the second region and the fourth region, wherein the optical lines are parallel to each other in the fourth region. A first transporting unit travels on the first rail. A second transporting unit travels on the second rail. A first controller controls the traveling of the first and second transporting units using light transmitted or received through the optical lines.Type: GrantFiled: September 21, 2017Date of Patent: August 21, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kun-Jin Ryu, Hyun-Min Lee, Youn-Boo Jung, Sung-Hyun Jo
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Patent number: 9972778Abstract: A method of forming a non-volatile memory device, includes forming a first electrode above a substrate, forming a dielectric layer overlying the first electrode, forming an opening structure in a portion of the dielectric layer to expose a surface of the first electrode having an aspect ratio, forming a resistive switching material overlying the dielectric layer and filling at least a portion of the opening structure using a deposition process, the resistive switching material having a surface region characterized by a planar region and an indent structure, the indent structure overlying the first electrode, maintaining a first thickness of resistive switching material between the planar region and the first electrode, maintaining a second thickness of resistive switching material between the indent structure and the first electrode, wherein the first thickness is larger than the second thickness, and forming a second electrode overlying the resistive switching material including the indent structure.Type: GrantFiled: December 17, 2014Date of Patent: May 15, 2018Assignee: CROSSBAR, INC.Inventor: Sung Hyun Jo
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Publication number: 20180062075Abstract: Providing for a two-terminal memory cell having intrinsic current limiting characteristic is described herein. By way of example, the two-terminal memory cell can comprise a particle donor layer having a moderate resistivity, comprised of unstable or partially unstable metal compounds. The metal compounds can be selected to release metal atoms in response to an external stimulus (e.g., an electric field, a voltage, a current, heat, etc.) into an electrically-resistive switching medium, which is at least in part permeable to drift or diffusion of the metal atoms. The metal atoms form a thin filament through the switching medium, switching the memory cell to a conductive state. The moderate resistivity of the particle donor layer in conjunction with the thin filament can result in an intrinsic resistance to current through the memory cell at voltages above a restriction voltage, protecting the memory cell from excessive current.Type: ApplicationFiled: August 14, 2017Publication date: March 1, 2018Inventors: Sung Hyun Jo, Xianliang Liu, Xu Zhao, Zeying Ren, FNU Atiquzzaman, Joanna Bettinger, Fengchiao Joyce Lin
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Publication number: 20180012783Abstract: A transporting system includes a first rail including a first region and a second region, the first region being a region where the first rail extends linearly and the second region being a region where the first rail is curved. A second rail includes a third region, separated from the first region, and a fourth region overlapping the second region, wherein the first and second rails merge at a joining location that includes the second region and the fourth region. Optical lines are disposed in the second region and the fourth region, wherein the optical lines are parallel to each other in the fourth region. A first transporting unit travels on the first rail. A second transporting unit travels on the second rail. A first controller controls the traveling of the first and second transporting units using light transmitted or received through the optical lines.Type: ApplicationFiled: September 21, 2017Publication date: January 11, 2018Inventors: KUN-JIN RYU, Hyun-Min Lee, Youn-Boo Jung, Sung-Hyun Jo
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Patent number: 9847130Abstract: Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.Type: GrantFiled: June 28, 2016Date of Patent: December 19, 2017Assignee: CROSSBAR, INC.Inventor: Sung Hyun Jo
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Patent number: 9805794Abstract: Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally provide a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, reduce wear or damage to the memory cell, or to improve Ion or Ioff distribution associated with changing the state of the memory cell.Type: GrantFiled: May 19, 2015Date of Patent: October 31, 2017Assignee: CROSSBAR, INC.Inventors: Zhi Li, Tanmay Kumar, Sung Hyun Jo
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Patent number: 9793147Abstract: A transporting system includes a first rail including a first region and a second region, the first region being a region where the first rail extends linearly and the second region being a region where the first rail is curved. A second rail includes a third region, separated from the first region, and a fourth region overlapping the second region, wherein the first and second rails merge at a joining location that includes the second region and the fourth region. Optical lines are disposed in the second region and the fourth region, wherein the optical lines are parallel to each other in the fourth region. A first transporting unit travels on the first rail. A second transporting unit travels on the second rail. A first controller controls the traveling of the first and second transporting units using light transmitted or received through the optical lines.Type: GrantFiled: May 16, 2016Date of Patent: October 17, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kun-Jin Ryu, Hyun-Min Lee, Youn-Boo Jung, Sung-Hyun Jo
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Patent number: 9793474Abstract: A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material.Type: GrantFiled: February 24, 2014Date of Patent: October 17, 2017Assignee: CROSSBAR, INC.Inventors: Xin Sun, Sung Hyun Jo, Tanmay Kumar
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Patent number: 9768234Abstract: Providing a high-density two-terminal memory architecture(s) having performance benefits of two-terminal memory and relatively low fabrication cost, is described herein. By way of example, the two-terminal memory architecture(s) can be constructed on a substrate, in various embodiments, and comprise two-terminal memory cells formed within conductive layer recess structures of the memory architecture. In one embodiment, a conductive layer recess can be created as a horizontal etch in conjunction with a vertical via etch. In another embodiment, the conductive layer recess can be patterned for respective conductive layers of the two-terminal memory architecture.Type: GrantFiled: March 9, 2015Date of Patent: September 19, 2017Assignee: CROSSBAR, INC.Inventor: Sung Hyun Jo
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Patent number: 9761635Abstract: Disclosed is a solid state memory having a non-linear current-voltage (I-V) response. By way of example, the solid state memory can be used as a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the nonvolatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.Type: GrantFiled: June 28, 2016Date of Patent: September 12, 2017Assignee: CROSSBAR, INC.Inventor: Sung Hyun Jo
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Patent number: 9735357Abstract: Providing for a two-terminal memory cell having intrinsic current limiting characteristic is described herein. By way of example, the two-terminal memory cell can comprise a particle donor layer having a moderate resistivity, comprised of unstable or partially unstable metal compounds. The metal compounds can be selected to release metal atoms in response to an external stimulus (e.g., an electric field, a voltage, a current, heat, etc.) into an electrically-resistive switching medium, which is at least in part permeable to drift or diffusion of the metal atoms. The metal atoms form a thin filament through the switching medium, switching the memory cell to a conductive state. The moderate resistivity of the particle donor layer in conjunction with the thin filament can result in an intrinsic resistance to current through the memory cell at voltages above a restriction voltage, protecting the memory cell from excessive current.Type: GrantFiled: February 1, 2016Date of Patent: August 15, 2017Assignee: CROSSBAR, INC.Inventors: Sung Hyun Jo, Xianliang Liu, Xu Zhao, Zeying Ren, Fnu Atiquzzaman, Joanna Bettinger, Fengchiao Joyce Lin
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Patent number: 9735358Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.Type: GrantFiled: April 20, 2016Date of Patent: August 15, 2017Assignee: CROSSBAR, INC.Inventors: Sung Hyun Jo, Kuk-Hwan Kim, Tanmay Kumar