Abstract: The present disclosure provides a polyimide film prepared from a precursor composition containing a polyamic acid and an organic solvent and having a value of (first FWHM?second FWHM)/(first FWHM+second FWHM) which is less than 0.4, a graphite sheet prepared from the polyimide film, and a method for preparing a graphite sheet.

Abstract: The present disclosure provides a polyimide film prepared from a precursor composition containing a polyamic acid and an organic solvent and having a value of (first FWHM?second FWHM)/(first FWHM+second FWHM) which is less than 0.4, a graphite sheet prepared from the polyimide film, and a method for preparing a graphite sheet.

Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.

Abstract: Provided are a plasma treatment apparatus and a method of fabricating semiconductor device using the same. The plasma treatment apparatus includes a chamber which provides a plasma treatment space, a bottom electrode disposed in the chamber and supports a wafer, a top electrode disposed in the chamber facing the bottom electrode, a source power source which supplies a source power output of a first frequency to the bottom electrode, a bias power source which supplies a bias power output of a second frequency different from the first frequency to the bottom electrode, and a pulse power source which applies a pulse voltage to the bottom electrode, wherein the bias power output is a bias voltage which is pulse-modulated to a first voltage level in a first time section and pulse-modulated to a second voltage level in a second time section and is applied to the bottom electrode.

Abstract: A jig for bonding a semiconductor chip may include a pressurizing portion and at least one opening. The pressuring portion may be configured to pressurize an upper surface of the semiconductor chip bonded to a package substrate via a bump and a flux using a laser. The opening may be surrounded by the pressurizing portion. The laser irradiated to the bump and the flux may be transmitted through the opening. A vapor generated from the flux by the laser may be discharged through the opening. Thus, the contamination of the jig caused by the vapor may be prevented so that a transmissivity of the laser through the jig may be maintained.

Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.

Abstract: The present invention relates to a polyimide film and a preparation method thereof. According to the present invention, a polyamic acid solution having a high weight-average molecular weight may be obtained by adjusting viscosity and solid content of the polyamic acid solution, and thus, a desired polyimide film may be prepared therefrom. Furthermore, since a length of carbon chains rearranged during graphitization is increased, a graphite sheet having excellent thermal conductivity can be prepared from the polyimide film of the present invention. Also, since the polyimide film has improved windability by further including inorganic particles as a filler, it may facilitate the wind operation.

Abstract: A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

Abstract: A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

Abstract: Disclosed are a display device and a control method thereof. The display device includes a display, a camera capturing a gesture in a three dimensional space; and a controller selectively displaying a virtual keyboard corresponding to a hand gesture for character input on the display when the captured gesture includes the hand gesture for the character input. Accordingly, the virtual keyboard corresponding to the hand gesture for the character input is displayed, so that the user may not perform an additional operation to display the virtual keyboard.

Abstract: A surface inspection apparatus and method of inspecting chip surfaces includes a laser generator that generates a periodic CW laser and is transformed into an inspection laser beam having a beam size smaller than a surface size of the chip. Thus, the inspection laser beam is irradiated onto a plurality of the semiconductor chips such that the semiconductor chips are partially and simultaneously heated. Thermal waves are detected in response to the inspection laser beam and thermal images are generated corresponding to the thermal waves. A surface image is generated by a lock-in thermography technique and hold exponent analysis of the thermal image, thereby generating surface image in which a surface defect is included. Time and accuracy of the surface inspection process is improved.

Abstract: A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads through a plurality of solders; a sealing layer configured to seal the chip and the solders, at least one void being between the solders; and a solder extrusion prevention layer on one sidewall of the solder exposed by the at least one void.

Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

Abstract: A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads through a plurality of solders; a sealing layer configured to seal the chip and the solders, at least one void being between the solders; and a solder extrusion prevention layer on one sidewall of the solder exposed by the at least one void.

Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.

Abstract: A surface inspection apparatus and method of inspecting chip surfaces includes a laser generator that generates a periodic CW laser and is transformed into an inspection laser beam having a beam size smaller than a surface size of the chip. Thus, the inspection laser beam is irradiated onto a plurality of the semiconductor chips such that the semiconductor chips are partially and simultaneously heated. Thermal waves are detected in response to the inspection laser beam and thermal images are generated corresponding to the thermal waves. A surface image is generated by a lock-in thermography technique and hold exponent analysis of the thermal image, thereby generating surface image in which a surface defect is included. Time and accuracy of the surface inspection process is improved.

Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.