Patents by Inventor Sung-IL Cho

Sung-IL Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8941165
    Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: January 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Cho, Seung-Young Son, Chang-Jin Kang, Kyeong-Koo Chi, Ji-Chul Shin
  • Patent number: 8901645
    Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
  • Publication number: 20140028567
    Abstract: Disclosed are a display device and a control method thereof. The display device includes a display, a camera capturing a gesture in a three dimensional space; and a controller selectively displaying a virtual keyboard corresponding to a hand gesture for character input on the display when the captured gesture includes the hand gesture for the character input. Accordingly, the virtual keyboard corresponding to the hand gesture for the character input is displayed, so that the user may not perform an additional operation to display the virtual keyboard.
    Type: Application
    Filed: April 19, 2011
    Publication date: January 30, 2014
    Applicant: LG ELECTRONICS INC.
    Inventors: Sung Jong Park, Kyung Jin Kim, Sae Hun Jang, Gu-Ang Jang, Sung Il Cho, Yooseok Cho, Jiyoung Hong
  • Publication number: 20130228856
    Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
    Type: Application
    Filed: April 17, 2013
    Publication date: September 5, 2013
    Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
  • Patent number: 8486787
    Abstract: A method of fabricating a semiconductor device includes forming a first contact opening having a relatively larger depth than a second contact opening to expose first and second contacts through an insulation layer, where the first and second contacts are located at different depths with respect to an upper surface of the insulation layer. Therefore, it is possible to prevent excessive over-etch of the second contact opening and minimize etching damage to the contact region exposed by the second contact opening.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: July 16, 2013
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Sung-Il Cho, Yoon-Jae Kim, Doo-Young Lee
  • Patent number: 8466074
    Abstract: A method for processing a substrate includes generating a first laser beam, splitting the first laser beam into a plurality of second laser beams, focusing the split second laser beams on a plane in the substrate parallel to a main surface of the substrate, and performing surface separation of the substrate along the plane.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: June 18, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-il Cho, Ho-tae Jin, Heui-seog Kim, Seon-ju Oh
  • Patent number: 8461687
    Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: June 11, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
  • Patent number: 8455854
    Abstract: A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: June 4, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Rae Cho, Sung-Il Cho, In-Kyeong Yoo, Eun-Hong Lee, Chang-Wook Moon
  • Patent number: 8314025
    Abstract: A method of forming a semiconductor device includes forming a lower conductive pattern on a substrate, forming an insulating layer over the lower conductive pattern, forming a contact hole through the insulating layer to expose the lower conductive pattern, forming a first spacer along sides of the contact hole, and then forming a contact plug in the contact hole. The contact plug is formed so as to contact the lower conductive pattern.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: November 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Cho, Nam-Gun Kim, Jong-Cheol Lee
  • Patent number: 8279659
    Abstract: A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: October 2, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Sung Il Cho, Sei Seung Yoon, Naveen Gundubogula, Mohamed H. Abu-Rahma, Dongkyu Park
  • Patent number: 8043926
    Abstract: A nonvolatile memory device includes at least one switching device and at least one storage node electrically connected to the at least one switching device. The at least one storage node includes a lower electrode, one or more oxygen-deficient metal oxide layers, one or more data storage layers, and an upper electrode. At least one of the one or more metal oxide layers is electrically connected to the lower electrode. At least one of the one or more data storage layers is electrically connected to at least one of the one or more metal oxide layers. The upper electrode is electrically connected to at least one of the one or more data storage layers. A method of manufacturing the nonvolatile memory device includes preparing the at least one switching device and forming the lower electrode, one or more metal oxide layers, one or more data storage layers, and upper electrode.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Cho, Choong-rae Cho, Eun-hong Lee, In-kyeong Yoo
  • Publication number: 20110256719
    Abstract: A method of fabricating a semiconductor device includes forming a first contact opening having a relatively larger depth than a second contact opening to expose first and second contacts through an insulation layer, where the first and second contacts are located at different depths with respect to an upper surface of the insulation layer. Therefore, it is possible to prevent excessive over-etch of the second contact opening and minimize etching damage to the contact region exposed by the second contact opening.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 20, 2011
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Nam-Gun Kim, Sung-Il Cho, Yoon-Jae Kim, Doo-Young Lee
  • Publication number: 20110256736
    Abstract: A method for processing a substrate includes generating a first laser beam, splitting the first laser beam into a plurality of second laser beams, focusing the split second laser beams on a plane in the substrate parallel to a main surface of the substrate, and performing surface separation of the substrate along the plane.
    Type: Application
    Filed: April 8, 2011
    Publication date: October 20, 2011
    Inventors: Sung-il Cho, Ho-tae Jin, Heui-seog Kim, Seon-ju Oh
  • Patent number: 8040118
    Abstract: A low-dropout (LDO) voltage regulator that includes an error amplifier which compares a reference voltage with a feedback voltage of an output voltage and outputs an error signal based on the result of the comparison, the error amplifier being biased by an input voltage; a first MOS transistor having a gate electrically connected to the error signal, a source electrically connected to the input voltage and a drain electrically connected to the output voltage; a voltage divider which transmits a predetermined part of the output voltage to the error amplifier as feedback voltage; and a level limiter which limits a level of the output voltage from changing beyond and below an offset voltage when a level of a load current changes. In accordance with embodiments, A predetermined number of comparators and MOS transistor type-switches are provided to enhance the slew ratio of the regulated output voltage and to reduce standby electricity consumption.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: October 18, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Sung-Il Cho, Sung-Man (Chang woo) Pang (Ha)
  • Publication number: 20110241102
    Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
    Type: Application
    Filed: March 28, 2011
    Publication date: October 6, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Cho, Nam-Gun Kim, Jin-Young Kim, Hyun-Chul Yoon, Bong-Soo Kim, Kwan-Sik Cho
  • Publication number: 20110183512
    Abstract: A method of forming a semiconductor device includes forming a lower conductive pattern on a substrate, forming an insulating layer over the lower conductive pattern, forming a contact hole through the insulating layer to expose the lower conductive pattern, forming a first spacer along sides of the contact hole, and then forming a contact plug in the contact hole. The contact plug is formed so as to contact the lower conductive pattern.
    Type: Application
    Filed: June 4, 2010
    Publication date: July 28, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Il Cho, Nam-Gun Kim, Jong-Cheol Lee
  • Publication number: 20110110174
    Abstract: A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 12, 2011
    Applicant: QUALCOMM INCORPORATED
    Inventors: Sung Il Cho, Sei Seung Yoon, Naveen Gundubogula, Mohamed H. Abu-Rahma, Dongkyu Park
  • Patent number: D682254
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: May 14, 2013
    Assignee: LG Electronics Inc.
    Inventors: Ji Young Hong, Gu Ang Jang, Jin Hae Choi, Kyung In Yang, Sung Il Cho
  • Patent number: D720768
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 6, 2015
    Assignee: LG Electronics Inc.
    Inventors: Ji Young Hong, Gu Ang Jang, Jin Hae Choi, Kyung In Yang, Sung Il Cho
  • Patent number: D721090
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: January 13, 2015
    Assignee: LG Electronics Inc.
    Inventors: Ji Young Hong, Gu Ang Jang, Jin Hae Choi, Kyung In Yang, Sung Il Cho