Abstract: In a semiconductor device including a transistor having an embedded gate, and methods of manufacturing the same, a substrate is divided into first and second regions. A gate trench is formed in the first region, a first gate structure partially fills the gate trench and a passivation layer pattern is provided inside the gate trench and positioned on the first gate structure. A first source/drain is provided adjacent to sidewalls of the first gate structure. A second gate structure is provided in the second region and has a silicon oxide layer, a conductive layer pattern and a metal silicide layer pattern stacked on the conductive layer pattern. A second source/drain is provided adjacent to sidewalls of the second gate structure. Defects due to formation of reactants may be reduced in a formation process of the above-described semiconductor device, improving reliability and operating characteristics.

Abstract: A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

Abstract: A method of manufacturing a semiconductor device having buried gates may include forming a stacked structure of sequentially stacked first mask patterns and second mask patterns with equal widths to expose active regions and isolation regions of a semiconductor substrate. After forming reduced first mask patterns by decreasing the width only of the first mask patterns, trenches may be formed in the active regions and the isolation regions by etching the exposed portions of the semiconductor substrate using the second mask patterns as an etch mask. Then, gate insulating films may be formed on inner walls of the trenches in the active regions, and a conductive material may be buried into the trenches in the active regions and the isolation regions to form gates.

Abstract: A method of forming a semiconductor device is provided. The method includes preparing a semiconductor substrate to include a cell region and a peripheral region and forming a first mask layer on the semiconductor substrate. First hard mask patterns that are configured to expose the first mask layer are formed on the first mask layer in the cell region. A second mask layer that is configured to conformably cover the first hard mask patterns is formed. A second hard mask pattern is formed between the first hard mask patterns, wherein the second hard mask pattern is configured to contact a lateral surface of the second mask layer. The second mask layer interposed between the first hard mask patterns and the second hard mask pattern is removed. A plurality of trenches are etched in the semiconductor substrate of the cell region using the first hard mask patterns and the second hard mask pattern as a mask.

Abstract: A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract: A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.

Abstract: Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

Abstract: A nonvolatile memory device includes at least one switching device and at least one storage node electrically connected to the at least one switching device. The at least one storage node includes a lower electrode, one or more oxygen-deficient metal oxide layers, one or more data storage layers, and an upper electrode. At least one of the one or more metal oxide layers is electrically connected to the lower electrode. At least one of the one or more data storage layers is electrically connected to at least one of the one or more metal oxide layers. The upper electrode is electrically connected to at least one of the one or more data storage layers. A method of manufacturing the nonvolatile memory device includes preparing the at least one switching device and forming the lower electrode, one or more metal oxide layers, one or more data storage layers, and upper electrode.

Abstract: A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a mold for forming a storage electrode, forming sacrificial spacers at side walls of openings in the mold, forming a conductive film for a storage electrode along the inside of the openings, removing the mold by a wet etching process, removing the sacrificial spacers by a dry etching process, and sequentially forming a dielectric film and an upper electrode on the storage electrode.

Abstract: An electrode structure having at least two oxide layers that more reliably switch and operate without the use of additional devices and a non-volatile memory device having the same are provided. The electrode structure may include a lower electrode, a first oxide layer formed on the lower electrode, a second oxide layer formed on the first oxide layer and an upper electrode formed on the second oxide layer wherein at least one of the first and second oxide layers may be formed of a resistance-varying material. The first oxide layer may be formed of an oxide having a variable oxidation state.

Abstract: A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.

Abstract: A transistor including a metal-insulation transition material and a method of manufacturing the same. The transistor including a metal-insulator transition material may include a substrate, a insulation layer formed on the substrate, a source region and a drain region separately formed from each other on the insulation layer, a tunneling barrier layer formed on at least one surface of the source region and the drain region, a metal-insulator transition material layer formed on the tunneling barrier layer and the insulation layer, a dielectric layer stacked on the metal-insulator transition material layer, and a gate electrode layer formed on the dielectric layer.

Abstract: A transistor using a physical property-changing layer, a method of operating the transistor, and a method of manufacturing the transistor are provided. The transistor may include an insulation layer formed on a substrate, the first and second conductive layer patterns, the physical property-changing layer, a dielectric layer, for example, a high dielectric layer, and a gate electrode. The first and second conductive layer patterns may be spaced apart from each other on the insulation layer. The physical property-changing layer may be formed on a portion of the insulation layer between the first and second conductive layer patterns. The dielectric layer may be stacked on the physical property-changing layer and the gate electrode may be formed on the high dielectric layer.

Abstract: A method of forming a capacitor can include etching a metal-nitride layer in an environment comprising fluorine and oxygen to form a capacitor electrode.

Abstract: A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

Abstract: A speaker having an improved sound-radiating function to both directions is provided. The speaker includes a magnetic circuit unit, a voice coil, and an auxiliary vibrating plate and a primary vibrating plate sequentially arranged from a forward direction. The voice coil vibrates toward a backward direction and a forward direction due to interaction with the magnetic circuit unit. The auxiliary vibrating plate is cone-shaped and has a damping function. The primary vibrating plate is also cone-shaped. Central necks of the primary vibrating plate and the auxiliary vibrating plate are fixed on the voice coil, respectively. The auxiliary vibrating plate is enlarged toward a forward direction and the primary vibrating plate is enlarged toward a backward direction.

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.