Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

Abstract: The present invention relates to an inverter device for a microgrid, and a method for controlling the same, the inverter device including: a waveform detector detecting a voltage waveform and a current waveform applied to a load; a control unit determining whether a sine wave appears based on the detected voltage waveform and the detected current waveform and performing voltage control or low order harmonic compensation depending on a determination result; and a switch generating a voltage waveform in a form of the sine wave by being turned on/off depending on a control signal received from the control unit and supplying the generated voltage waveform in the form of the sine wave to the load.

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

Abstract: A vehicle according to an exemplary embodiment of the present invention includes an electronic chassis control system configured for an electronic control suspension (ECS), a motor driven power steering system (MDPS), an electronic stability control (ESC), and an all wheel drive (AWD), and an integrated controller implementing an integrated avoidance control in which controls for each of the MDPS, the ESC, and the AWD according to an emergency avoidance control of the ECS in the forward collision situation, wherein it is possible to safely and rapidly avoid risk of forward collision, and cooperative control performance of the ECS and the AWD, the ESC and the MDPS is optimized by applying an emergency grade to the integrated avoidance control.

Abstract: A method of controlling driving of a vehicle using an in-wheel system includes determining whether the vehicle enters a steering avoidance section, based on driving information of the vehicle, verifying a detailed or specific section in the steering avoidance section in which the vehicle is located when the vehicle enters the steering avoidance section, and controlling torque of a motor mounted in each wheel to satisfy a yaw moment required in the verified detailed section.

Abstract: In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.

Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

Abstract: A solid state drive (SSD) package type has a lower package including a lower package substrate, a controller chip mounted on the lower package substrate, and a plurality of upper packages disposed on the lower package as spaced apart from each other. The plurality of upper packages includes at least one non-volatile memory and at least one first individual electronic component. The upper packages are electrically connected to the lower package such that the package type is a package-on-package (PoP) type. The height of the first individual electronic component is greater than the spacing between the lower package and each of the upper packages.

Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package.

Abstract: A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.

Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

Abstract: A method for manufacturing a semiconductor device includes generating a layout including a first conductive pattern region and a second conductive pattern region. A first interlayer insulating film is formed on a substrate, the first interlayer insulating film including a first region corresponding to the first conductive pattern region, a second region corresponding to the second conductive pattern region, and a third region spaced apart from the first and second regions and disposed between the first and second regions. First, second and third lower metal wirings are formed to respectively fill the first, second and third recesses of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film. A first dummy via hole is formed in the second interlayer insulating film to expose the third lower metal wiring. The third lower metal wiring is electrically isolated.

Abstract: A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines.

Abstract: A method for manufacturing a semiconductor device includes generating a layout including a first conductive pattern region and a second conductive pattern region. A first interlayer insulating film is formed on a substrate, the first interlayer insulating film including a first region corresponding to the first conductive pattern region, a second region corresponding to the second conductive pattern region, and a third region spaced apart from the first and second regions and disposed between the first and second regions. First, second and third lower metal wirings are formed to respectively fill the first, second and third recesses of the first interlayer insulating film. A second interlayer insulating film is formed on the first interlayer insulating film. A first dummy via hole is formed in the second interlayer insulating film to expose the third lower metal wiring. The third lower metal wiring is electrically isolated.

Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.

Abstract: A method of forming a mask layout includes forming a layout of a first mask including a lower wiring structure pattern and a dummy lower wiring structure pattern. A layout of a second mask overlapping the first mask and including an upper wiring structure pattern and a dummy upper wiring structure pattern is formed. A layout of a third mask including a first via structure pattern and a first dummy via structure pattern is formed. A layout of a fourth mask including a second via structure pattern and a second dummy via structure pattern is formed. The second via structure pattern may commonly overlap the lower wiring structure pattern and the upper wiring structure pattern, and the second dummy via structure pattern may commonly overlap the dummy lower wiring structure pattern and the dummy upper wiring structure pattern. The fourth mask may overlap the third mask.

Abstract: A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.

Abstract: The inventive concept provides methods for forming fine patterns of a semiconductor device. The method includes forming a buffer mask layer having first holes on a hard mask layer including a first region and a second region around the first region, forming first pillars filling the first holes and disposed on the buffer mask layer in the first region and second pillars disposed on the buffer mask layer in the second region, forming a block copolymer layer covering the first and second pillars on the buffer mask layer, phase-separating the block copolymer layer to form first block patterns spaced apart from the first and second pillars and a second block pattern surrounding the first and second pillars and the first block patterns, removing the first block patterns, and forming second holes in the buffer mask layer under the first block patterns.