Patents by Inventor Swaroop Kaza
Swaroop Kaza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923019Abstract: The present disclosure provides for improving data retention reliability. During a programming operation associated with a memory cell, after the memory cell passes verification of a first verification voltage level, a second verification voltage level can be applied to the memory cell. Based on a comparison of the voltage in the memory cell with the second verification voltage level, a bit line voltage may be applied. Based on the applied bit line voltage, fast bits associated with the memory cell can be upshifted to an upper portion of a final voltage distribution associated with the programming operation. Upshifting the fast bits counteracts the downshifting effect in a final voltage distribution that may be caused by charge leakage or electron loss.Type: GrantFiled: February 14, 2022Date of Patent: March 5, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Xiaojia Jia, Swaroop Kaza, Laidong Wang, Jiacen Guo
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Patent number: 11862260Abstract: Read disturb audit techniques that include algorithmically applying audit verify voltages to erased wordlines in an open memory block are described. In an audit verify technique, a pass-through voltage ensured to be higher than any threshold voltage of any cell is applied to each wordline in an open memory block that includes one or more programmed memory cells, and an audit verify voltage lower than the pass-through voltage is applied to each erased wordline. A first bit count representing a number of non-conductive bitline(s) is determined and compared to a threshold value to determine whether to continue or discontinue block operation. In an audit verify and audit gap technique, the erased wordlines are divided into disjoint first and second groups, and an audit verify voltage and a non-verify voltage are alternatively applied to the groups in different audit verify stages.Type: GrantFiled: February 14, 2022Date of Patent: January 2, 2024Assignee: SANDISK TECHNOLOGIES LLCInventors: Jiacen Guo, Swaroop Kaza
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Publication number: 20230260583Abstract: The present disclosure provides for improving data retention reliability. During a programming operation associated with a memory cell, after the memory cell passes verification of a first verification voltage level, a second verification voltage level can be applied to the memory cell. Based on a comparison of the voltage in the memory cell with the second verification voltage level, a bit line voltage may be applied. Based on the applied bit line voltage, fast bits associated with the memory cell can be upshifted to an upper portion of a final voltage distribution associated with the programming operation. Upshifting the fast bits counteracts the downshifting effect in a final voltage distribution that may be caused by charge leakage or electron loss.Type: ApplicationFiled: February 14, 2022Publication date: August 17, 2023Inventors: Xiaojia JIA, Swaroop KAZA, Laidong WANG, Jiacen GUO
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Publication number: 20230260584Abstract: Read disturb audit techniques that include algorithmically applying audit verify voltages to erased wordlines in an open memory block are described. In an audit verify technique, a pass-through voltage ensured to be higher than any threshold voltage of any cell is applied to each wordline in an open memory block that includes one or more programmed memory cells, and an audit verify voltage lower than the pass-through voltage is applied to each erased wordline. A first bit count representing a number of non-conductive bitline(s) is determined and compared to a threshold value to determine whether to continue or discontinue block operation. In an audit verify and audit gap technique, the erased wordlines are divided into disjoint first and second groups, and an audit verify voltage and a non-verify voltage are alternatively applied to the groups in different audit verify stages.Type: ApplicationFiled: February 14, 2022Publication date: August 17, 2023Inventors: JIACEN GUO, Swaroop Kaza
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Publication number: 20230197174Abstract: A memory device with adaptive sense time tables is disclosed. In order to maintain a desired (initial or preset) threshold voltage distribution, the sense time is adjusted as the program-erase cycle count increases. The program-erase cycle process tends to wear down memory cells, causing the QPW window to expand and the threshold voltage to widen. However, by adjusting (i.e., reducing) the sense time for increased program-erase cycles, the QPW window and the threshold voltage can be at least substantially maintained. Additionally, systems and methods for adjusting sense time based on die-to-die variations are also disclosed.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: SanDisk Technologies LLCInventors: Jiacen GUO, Xiang YANG, Swaroop KAZA, Laidong WANG
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Patent number: 11475958Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.Type: GrantFiled: March 4, 2021Date of Patent: October 18, 2022Assignee: SanDisk Technologies LLCInventors: Yu-Chung Lien, Huai-yuan Tseng, Swaroop Kaza, Tomer Eliash
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Publication number: 20220284965Abstract: A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.Type: ApplicationFiled: March 4, 2021Publication date: September 8, 2022Applicant: SanDisk Technologies LLCInventors: Yu-Chung Lien, Huai-yuan Tseng, Swaroop Kaza, Tomer Eliash
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Patent number: 10734084Abstract: A non-volatile storage system comprises non-volatile memory cells arranged in physical blocks, and one or more control circuits in communication with the non-volatile memory cells. The one or more control circuits are configured to write data to a physical block of the non-volatile memory cells with a scheme to reduce read disturb if a logical block associated with the physical block has a read intensity greater than a threshold.Type: GrantFiled: May 31, 2019Date of Patent: August 4, 2020Assignee: Western Digital Technologies, Inc.Inventors: Narayan Kuddannavar, Swaroop Kaza, Sainath Viswasarai
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Patent number: 10643710Abstract: Apparatuses, systems, methods, and computer program products for enhanced erase retry of a non-volatile storage device are disclosed. An apparatus includes a non-volatile storage device and a controller. A controller includes a verification component configured to detect that an erase operation performed on an erase block of a non-volatile storage device is unsuccessful. A controller includes a parameter component configured to adjust one or more erase parameters for an erase operation. One or more erase parameters may be associated with one or more select gate drain storage cells of an erase block. A controller includes an erase component configured to retry an erase operation on an erase block with one or more adjusted erase parameters.Type: GrantFiled: November 30, 2017Date of Patent: May 5, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Divya Prasad, Sainath Viswasarai, Gopu S, Swaroop Kaza, Piyush Anil Dhotre, Chittoor Devarajan Sunilkumar
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Publication number: 20190371416Abstract: A non-volatile storage system comprises non-volatile memory cells arranged in physical blocks, and one or more control circuits in communication with the non-volatile memory cells. The one or more control circuits are configured to write data to a physical block of the non-volatile memory cells with a scheme to reduce read disturb if a logical block associated with the physical block has a read intensity greater than a threshold.Type: ApplicationFiled: May 31, 2019Publication date: December 5, 2019Applicant: Western Digital Technologies, Inc.Inventors: Narayan Kuddannavar, Swaroop Kaza, Sainath Viswasarai
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Publication number: 20190164614Abstract: Apparatuses, systems, methods, and computer program products for enhanced erase retry of a non-volatile storage device are disclosed. An apparatus includes a non-volatile storage device and a controller. A controller includes a verification component configured to detect that an erase operation performed on an erase block of a non-volatile storage device is unsuccessful. A controller includes a parameter component configured to adjust one or more erase parameters for an erase operation. One or more erase parameters may be associated with one or more select gate drain storage cells of an erase block. A controller includes an erase component configured to retry an erase operation on an erase block with one or more adjusted erase parameters.Type: ApplicationFiled: November 30, 2017Publication date: May 30, 2019Applicant: Western Digital Technologies, Inc.Inventors: DIVYA PRASAD, SAINATH VISWASARAI, GOPU S, SWAROOP KAZA, PIYUSH ANIL DHOTRE, CHITTOOR DEVARAJAN SUNILKUMAR
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Patent number: 10235294Abstract: Apparatuses and techniques are described for performing a pre-read operation in preparation for a read operation in a memory device. The pre-read operation transitions the memory cells from a first read condition to a second read condition so that their threshold voltages will be in a desired, predictable range when the read occurs. The pre-read operation can involve maintaining voltages on a selected word line and unselected word lines at specified levels and for a specified duration which is relatively long compared to a duration of the read operation. The word line voltages, in combination with bit line and source line voltages, provide the channels of a NAND string in a conductive state and gradually transitions the memory cells to the second read condition.Type: GrantFiled: April 23, 2018Date of Patent: March 19, 2019Assignee: SanDisk Technologies LLCInventors: Ching-Huang Lu, Swaroop Kaza, Piyush Sagdeo
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Patent number: 9449690Abstract: A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level.Type: GrantFiled: April 3, 2013Date of Patent: September 20, 2016Assignee: Cypress Semiconductor CorporationInventors: Swaroop Kaza, Youseok Suh, Di Li, Sameer S. Haddad
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Patent number: 9012299Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: GrantFiled: August 14, 2014Date of Patent: April 21, 2015Assignee: Spansion LLCInventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dong-Xiang Liao, Wai Lo, Christie Marrian, Sameer Haddad
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Publication number: 20140357044Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. in alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: ApplicationFiled: August 14, 2014Publication date: December 4, 2014Inventors: Steven AVANZINO, Tzu-Ning FANG, Swaroop KAZA, Dong-Xiang LIAO, Wai LO, Christie MARRIAN, Sameer HADDAD
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Publication number: 20140301146Abstract: A method of programming a memory system by selectively applying a program voltage to a selected wordline connected to a memory transistor to be programmed. A first bias voltage is applied to a first wordline adjacent to the source side of the selected wordline. The first bias voltage is also applied to a second wordline adjacent to the drain side of the selected wordline. A second bias voltage is applied to a third wordline adjacent to the drain side of the second wordline. A third bias voltage is applied to a fourth wordline adjacent to the source side of the first wordline. A pass voltage is also applied to the remaining wordlines that do not have one of a bias voltage and a program voltage applied, the pass voltage a selected voltage level.Type: ApplicationFiled: April 3, 2013Publication date: October 9, 2014Applicant: Spansion LLCInventors: Swaroop KAZA, Youseok SUH, Di LI, Sameer HADDAD
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Patent number: 8828837Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: GrantFiled: April 19, 2013Date of Patent: September 9, 2014Assignee: Spansion LLCInventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dongxiang Liao, Wai Lo, Christie Marrian, Sameer Haddad
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Publication number: 20130237030Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: ApplicationFiled: April 19, 2013Publication date: September 12, 2013Applicant: Spansion LLCInventors: Steven AVANZINO, Tzu-Ning FANG, Swaroop KAZA, Dongxiang LIAO, Wai LO, Christie MARRIAN, Sameer HADDAD
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Patent number: 8482959Abstract: A method of repairing a memory device is provided. If an erase process is unsuccessful, a repair process is performed. A programmed state of the memory device is determined, A subsequent erase process dependent on the programmed state is performed. Also, a method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor.Type: GrantFiled: December 13, 2011Date of Patent: July 9, 2013Assignee: Spansion LLCInventors: Swaroop Kaza, Sameer Haddad
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Patent number: 8445913Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: GrantFiled: October 30, 2007Date of Patent: May 21, 2013Assignee: Spansion LLCInventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dongxiang Liao, Wai Lo, Christie Marrian, Sameer Haddad