Patents by Inventor Swaroop Kaza
Swaroop Kaza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8445913Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: GrantFiled: October 30, 2007Date of Patent: May 21, 2013Assignee: Spansion LLCInventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dongxiang Liao, Wai Lo, Christie Marrian, Sameer Haddad
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Publication number: 20120081983Abstract: A method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor.Type: ApplicationFiled: December 13, 2011Publication date: April 5, 2012Inventors: Swaroop KAZA, Sameer HADDAD
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Patent number: 8077495Abstract: A method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor.Type: GrantFiled: December 5, 2006Date of Patent: December 13, 2011Assignee: Spansion LLCInventors: Swaroop Kaza, Sameer Haddad
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Patent number: 7916523Abstract: In a first method of erasing a resistive memory device, an electrical potential is applied to the gate of a transistor in series with the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials across the resistive memory device. In a second method of erasing a resistive memory device, an electrical potential is applied across the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials to the gate of a transistor in series with the resistive memory device.Type: GrantFiled: December 5, 2006Date of Patent: March 29, 2011Assignee: Spansion LLCInventors: An Chen, Sameer Haddad, Yi-Ching Jean Wu, Swaroop Kaza
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Patent number: 7902086Abstract: Improving memory retention properties of a polymer memory cell are disclosed. The methods include providing a semiconducting polymer layer containing at least one organic semiconductor and at least one of a carrier ion oxidation preventer and an electrode oxidation preventer. The oxidation preventers may contain at least one of 1) an oxygen scavenger, 2) a polymer with oxidizable side-chain groups which can be preferentially oxidized over the carrier ions/electrodes, and 3) an oxidizable molecule that can be preferentially oxidized over the carrier ions/electrodes.Type: GrantFiled: December 8, 2006Date of Patent: March 8, 2011Assignee: Spansion LLCInventors: Swaroop Kaza, David Gaun, Michael A. Van Buskirk
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Patent number: 7706168Abstract: The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.Type: GrantFiled: October 30, 2007Date of Patent: April 27, 2010Assignee: Spansion LLCInventors: Tzu-Ning Fang, Steven Avanzino, Swaroop Kaza, Dongxiang Liao, Christie Marrian, Sameer Haddad
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Patent number: 7646624Abstract: In a method of providing an operating characteristic of a resistive memory device, material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device to form a reaction layer, the selected operating characteristic being dependent on the presence of the reaction layer.Type: GrantFiled: October 31, 2006Date of Patent: January 12, 2010Assignee: Spansion LLCInventors: Tzu-Ning Fang, Swaroop Kaza, An Chen, Sameer Haddad
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Patent number: 7579631Abstract: A memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes is disclosed. The controllably conductive media includes a passive layer made of super ionic material and an active layer. When an external stimuli, such as an applied electric field, is imposed upon the first and second electrode, ions move and dope and/or de-dope the polymer. The applied external stimuli used to dope the polymer is larger than an applied external stimuli to operate the memory cell. The polymer functions as a variable breakdown characteristic diode with electrical characteristics which are a consequence of the doping degree. The memory element may have a current limited read signal. Methods of making the memory devices/cells, methods of using the memory devices/cells, and devices such as computers, hand-held electronic devices and memory devices containing the memory cell(s) are also disclosed.Type: GrantFiled: March 22, 2005Date of Patent: August 25, 2009Assignee: Spansion LLCInventors: David Gaun, Colin S. Bill, Swaroop Kaza
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Patent number: 7564708Abstract: In a memory device having first and second electrodes and active and passive layers between the electrodes, or a memory device having first and second electrodes and an insulating layer between and in contact with electrodes, the device may be programmed in the ionic mode by applying electrical potential across the electrodes in one direction, and may be programmed in the electronic charge carrier mode by applying electrical potential across electrodes in the opposite direction.Type: GrantFiled: December 5, 2006Date of Patent: July 21, 2009Assignee: Spansion LLCInventors: Tzu-Ning Fang, Michael VanBuskirk, Swaroop Kaza
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Publication number: 20090109598Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dongxiang Liao, Wai Lo, Christie Marrian, Sameer Haddad
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Publication number: 20090109727Abstract: The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Inventors: Tzu-Ning Fang, Steven Avanzino, Swaroop Kaza, Dongxiang Liao, Christie Marrian, Sameer Haddad
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Patent number: 7474579Abstract: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.Type: GrantFiled: December 20, 2006Date of Patent: January 6, 2009Assignee: Spansion LLCInventors: Colin S. Bill, Swaroop Kaza, Wei Daisy Cai, Tzu-Ning Fang, David Gaun, Eugen Gershon, Michael A. Van Buskirk, Jean Wu
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Patent number: 7450416Abstract: The present invention is a method of undertaking a procedure on a memory-diode, wherein a memory-diode is provided which is programmable so as to have each of a plurality of different threshold voltages. A reading of the state of the memory-diode indicates the so determined threshold voltage of the memory-diode.Type: GrantFiled: December 23, 2004Date of Patent: November 11, 2008Assignee: Spansion LLCInventors: Swaroop Kaza, Juri Krieger, David Gaun, Stuart Spitzer, Richard Kingsborough, Zhida Lan, Colin S. Bill, Wei Daisy Cai, Igor Sokolik
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Publication number: 20080151669Abstract: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Applicant: SPANSION LLCInventors: Colin S. Bill, Swaroop Kaza, Wei Daisy Cai, Tzu-Ning Fang, David Gaun, Eugen Gershon, Michael A. Van Buskirk, Jean Wu
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Publication number: 20080135834Abstract: Improving memory retention properties of a polymer memory cell are disclosed. The methods include providing a semiconducting polymer layer containing at least one organic semiconductor and at least one of a carrier ion oxidation preventer and an electrode oxidation preventer. The oxidation preventers may contain at least one of 1) an oxygen scavenger, 2) a polymer with oxidizable side-chain groups which can be preferentially oxidized over the carrier ions/electrodes, and 3) an oxidizable molecule that can be preferentially oxidized over the carrier ions/electrodes.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Applicant: SPANSION LLCInventors: Swaroop Kaza, David Gaun, Michael A. Van Buskirk
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Publication number: 20080133818Abstract: A method of programming and erasing a memory device is provided. The memory device includes first and second electrodes and a switching layer therebetween. A first on-state resistance characteristic of the memory device is provided in programming the memory device by application of a first voltage to the gate of a transistor in series with the memory device. Other on-state resistance characteristics of the memory device, different from the first on-state resistance characteristic, may be provided by application of other voltages, different from the first voltage, to the gate of the transistor.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Inventors: Swaroop Kaza, Sameer Haddad
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Publication number: 20080130392Abstract: In a first method of erasing a resistive memory device, an electrical potential is applied to the gate of a transistor in series with the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials across the resistive memory device. In a second method of erasing a resistive memory device, an electrical potential is applied across the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials to the gate of a transistor in series with the resistive memory device.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Inventors: An Chen, Sameer Haddad, Yi-Ching Jean Wu, Swaroop Kaza
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Publication number: 20080130357Abstract: In a memory device having first and second electrodes and active and passive layers between the electrodes, or a memory device having first and second electrodes and an insulating layer between and in contact with electrodes, the device may be programmed in the ionic mode by applying electrical potential across the electrodes in one direction, and may be programmed in the electronic charge carrier mode by applying electrical potential across electrodes in the opposite directionType: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Inventors: Tzu-Ning Fang, Michael VanBuskirk, Swaroop Kaza
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Patent number: 7378682Abstract: The present memory device has first and second electrodes, a passive layer between the first and second electrodes and on and in contact with the first electrode, and an active layer between the first and second electrodes and on and in contact with the passive layer and second electrode, for receiving a charged specie from the passive layer. The active layer is a mixture of (i) a first polymer, and (ii) a second polymer for enhancing ion transport, improving the interface and promoting a rapid and substantially uniform distribution of the charged specie in the active layer, i.e., preventing a localized injection of the charged species. These features result in a memory element with improved stability, a more controllable ON-state resistance, improved switching speed and a lower programming voltage.Type: GrantFiled: February 7, 2005Date of Patent: May 27, 2008Assignee: Spanson LLCInventors: David Gaun, Swaroop Kaza, Stuart Spitzer, Juri Krieger, Richard Kingsborough
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Patent number: 7379317Abstract: A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.Type: GrantFiled: December 23, 2004Date of Patent: May 27, 2008Assignee: Spansion LLCInventors: Colin S. Bill, Swaroop Kaza, Tzu-Ning Fang, Stuart Spitzer