Abstract: A circuit is disclosed that includes a first differential input pair, a second differential input pair, a first switch, and a second switch. The first differential input pair receives an output voltage at an output node and a first temperature-dependent voltage. The second differential input pair receives the output voltage and a second temperature-dependent voltage. When the output voltage reaches the second temperature-dependent voltage, the first switch is turned on to pull up the output voltage in response to a first control signal generated according to an output signal of the second differential input pair. When the output voltage reaches the first temperature-dependent voltage, the second switch is turned on to pull down the output voltage in response to a second control signal generated according to an output signal of the first differential input pair.

Abstract: A decoupling capacitance (decap) system which includes: a decap circuit electrically coupled between a first or second reference voltage rail and a first node; and a biasing circuit coupled between the first node and correspondingly the second or first reference voltage rail. Due to the series connection between the decap circuit and the biasing circuit, the voltage drop across the biasing circuit effectively reduces the voltage drop across the decap circuit so that the voltage drop across the decap circuit is less than a voltage drop across the decap system as whole.

Abstract: An IC device includes first and second resistors. The first resistor includes first and second metal segments extending in a first direction in a first metal layer, and a third metal segment extending in a second direction in a second metal layer, and electrically connecting the first and second metal segments. The second resistor includes fourth and fifth metal segments extending in the first direction in the first metal layer, and a sixth metal segment extending in the second direction in a third metal layer, and electrically connecting the fourth and fifth metal segments. The fourth and fifth metal segment have a width greater than a width of the first and second metal segments, the fourth metal segment is between the first and second metal segments and separated from the first metal segment by a distance, and a fourth and fifth metal segment separation is greater than the distance.

Abstract: A semiconductor device includes a temperature-independent current generator that generates a reference current substantially independent of temperature and a mirror current that is a substantial duplicate of the reference current, a pulse signal generator that samples the mirror current so as to generate a pulse signal, and a counter that obtains a number of pulse signals generated by the pulse signal generator, that permits the pulse signal generator to generate a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is less than a predetermined threshold value, and that inhibits the pulse signal generator from generating a pulse signal when it is determined thereby that the number of pulse signals obtained thereby is equal to the predetermined threshold value. A method for monitoring a temperature of the semiconductor device is also disclosed.

Abstract: A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.

Abstract: A semiconductor device includes a substrate and a plurality of source/drain (S/D) regions in the substrate, wherein each of the plurality of S/D regions includes a first dopant having a first dopant type, and the each of the plurality of S/D regions are electrically coupled together. The semiconductor device further includes a gate stack over the substrate. The semiconductor device further includes a channel region in the substrate, wherein the channel region is below the gate stack and between adjacent S/D regions of the plurality of S/D regions, the channel region includes a second dopant having the first dopant type, and a concentration of the second dopant in the channel region is less than a concentration of the first dopant in each of the plurality of S/D regions.

Abstract: A method of calibrating a thermal sensor device is provided. The method includes extracting an incremental voltage to temperature curve for a diode array from a first incremental voltage of the diode array at a first temperature. The diode array and a device under test (DUT) which includes a thermal sensor are heated. After heating the diode array, a first incremental temperature is determined from the incremental voltage to temperature curve for the diode array and a second incremental voltage of the diode array after heating the diode array. An incremental voltage to temperature curve is extracted for the DUT from the first incremental temperature, a first incremental voltage for the DUT at the first temperature, and a second incremental voltage of the DUT after heating the device under test. A temperature error for the thermal sensor is determined from the incremental voltage to temperature curve for the DUT.

Abstract: A thermal sensor in some embodiments comprises two temperature-sensitive branches, each including a thermal-sensing device, such as one or more bipolar-junction transistors, and a current source for generating a current density in the thermal-sensing device to generate a temperature-dependent signal. The thermal sensor further includes a signal processor configured to multiply the temperature-dependent signal from the branches by respective and different gain factors, and combine the resultant signals to generate an output signal that is substantially proportional to the absolute temperature the thermal sensor is disposed at.

Abstract: An integrated circuit includes a first metal-insulator-semiconductor capacitor, a second metal-insulator-semiconductor capacitor, and a metal-insulator-metal capacitor. A first terminal of the first metal-insulator-semiconductor capacitor is configured to receive a first reference voltage for a higher voltage domain, while a first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second reference voltage for the higher voltage domain. A second terminal of the first metal-insulator-semiconductor capacitor is conductively connected to a first terminal of the metal-insulator-metal capacitor, while a second terminal of the second metal-insulator-semiconductor capacitor is conductively connected to a second terminal of the metal-insulator-metal capacitor.

Abstract: A thermal sensor in some embodiments comprises two temperature-sensitive branches, each including a thermal-sensing device, such as one or more bipolar-junction transistors, and a current source for generating a current density in the thermal-sensing device to generate a temperature-dependent signal. The thermal sensor further includes a signal processor configured to multiply the temperature-dependent signal from the branches by respective and different gain factors, and combine the resultant signals to generate an output signal that is substantially proportional to the absolute temperature the thermal sensor is disposed at.

Abstract: A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Abstract: A method of calibrating a thermal sensor device is provided. The method includes extracting an incremental voltage to temperature curve for a diode array from a first incremental voltage of the diode array at a first temperature. The diode array and a device under test (DUT) which includes a thermal sensor are heated. After heating the diode array, a first incremental temperature is determined from the incremental voltage to temperature curve for the diode array and a second incremental voltage of the diode array after heating the diode array. An incremental voltage to temperature curve is extracted for the DUT from the first incremental temperature, a first incremental voltage for the DUT at the first temperature, and a second incremental voltage of the DUT after heating the device under test. A temperature error for the thermal sensor is determined from the incremental voltage to temperature curve for the DUT.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

Abstract: A decoupling capacitance (decap) system which includes: a decap circuit electrically coupled between a first or second reference voltage rail and a first node; and a biasing circuit coupled between the first node and correspondingly the second or first reference voltage rail. Due to the series connection between the decap circuit and the biasing circuit, the voltage drop across the biasing circuit effectively reduces the voltage drop across the decap circuit so that the voltage drop across the decap circuit is less than a voltage drop across the decap system as whole.

Abstract: A circuit is disclosed that includes a first differential input pair, a second differential input pair, a first switch, and a second switch. The first differential input pair receives an output voltage at an output node and a first temperature-dependent voltage. The second differential input pair receives the output voltage and a second temperature-dependent voltage. When the output voltage reaches the second temperature-dependent voltage, the first switch is turned on to pull up the output voltage in response to a first control signal generated according to an output signal of the second differential input pair. When the output voltage reaches the first temperature-dependent voltage, the second switch is turned on to pull down the output voltage in response to a second control signal generated according to an output signal of the first differential input pair.

Abstract: A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.

Abstract: A circuit is disclosed that includes a capacitive element, a control circuit, and a first switch and a second switch. The capacitive element is configured to generate an output voltage at a terminal thereof. The control circuit is configured to generate a first control signal and a second control signal in response to a first temperature-dependent voltage, a second temperature-dependent voltage, and the output voltage. The first switch and the second switch are coupled to the capacitive element, and configured to be turned on or off in response to the first control signal and the second control signal respectively. The first switch and the second switch have different switching status from each other in a charge mode.

Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.

Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.