Patents by Inventor Szu-Lin LIU
Szu-Lin LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180073934Abstract: A circuit is disclosed that includes a first differential input pair, a second differential input pair, and a capacitive element. The first differential input pair is configured to be activated according to an output of the second differential input pair, and the second differential input pair is configured to be activated according to an output of the first differential input pair. The first differential input pair and the second differential input pair each comprises an input configured to receive an output signal. The capacitive element configured to be charged according to the output of the first differential input pair, and configured to be discharged according to the output of the second differential input pair, in order to generate the output signal.Type: ApplicationFiled: November 20, 2017Publication date: March 15, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jaw-Juinn HORNG, Szu-Lin LIU
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Publication number: 20180006163Abstract: A metal-oxide-semiconductor (MOS) capacitor is disclosed. The MOS capacitor includes a front-end-of-the-line (FEOL) field effect transistor (FET), and a plurality of middle-end-of-the-line (MEOL) conductive structures. The FEOL FET includes a source region and a drain region positioned in a semiconductor substrate, and a gate over the semiconductor substrate. The plurality of MEOL conductive structures is disposed on a top surface of the gate. At least one of the MEOL conductive structures is electrically disconnected from a back-end-of-the-line (BEOL) metal layer. A semiconductor fabrication method and a MOS capacitor circuit are also disclosed.Type: ApplicationFiled: July 1, 2016Publication date: January 4, 2018Inventors: SZU-LIN LIU, JAW-JUINN HORNG, YUNG-CHOW PENG
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Patent number: 9841326Abstract: A circuit is disclosed that includes a first differential input pair and a second differential input pair. The first differential input pair is activated according to an output of the second differential input pair, and receives a first temperature-dependent voltage and an output signal. The second differential input pair is activated according to an output of the first differential input pair, and receives a second temperature-dependent voltage and the output signal. The switching circuit couples a capacitive element to a first voltage supply according to the output of the first differential input pair, and the capacitive element to a second voltage supply according to the output of the second differential input pair, to generate the output signal.Type: GrantFiled: November 19, 2015Date of Patent: December 12, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jaw-Juinn Horng, Szu-Lin Liu
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Patent number: 9804220Abstract: Some embodiments of the present disclosure provide a method including turning on a noise-measuring system for a device under test (DUT) with the DUT turned off; measuring a first phase noise caused by the noise-measuring system; turning on the DUT; measuring a second phase noise caused by the noise-measuring system and the DUT; and subtracting the first phase noise from the second phase noise to obtain a third phase noise caused by the DUT.Type: GrantFiled: May 18, 2015Date of Patent: October 31, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jaw-Juinn Horng, Szu-Lin Liu, Jinn-Yeh Chien
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Publication number: 20170299442Abstract: A circuit includes a first current source that provides a current and a resistive branch in series with the first current source that provides a first voltage value and a second voltage value. A capacitive device is coupled with a voltage node having a voltage value, and a switching network alternates between charging the capacitive device to have the voltage value increase to the first voltage value, and discharging the capacitive device to have the voltage value decrease to the second voltage value.Type: ApplicationFiled: June 30, 2017Publication date: October 19, 2017Inventors: Jaw-Juinn HORNG, Szu-Lin LIU, Chung-Hui CHEN
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Patent number: 9702763Abstract: A circuit includes a comparator unit and a switching network. The comparator unit is configured to receive a first voltage value, a second voltage value and a third voltage value of a voltage node, and to provide a control signal. The switching network includes the voltage node and is configured to operate in a first condition or in a second condition based on the control signal. Based on the first condition, the voltage node is configured to have a voltage value increase to the first voltage value. Based on a second condition, the voltage node is configured to have a voltage decrease to the second voltage.Type: GrantFiled: June 17, 2013Date of Patent: July 11, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jaw-Juinn Horng, Szu-Lin Liu, Chung-Hui Chen
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Publication number: 20170184459Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.Type: ApplicationFiled: March 15, 2017Publication date: June 29, 2017Inventors: Szu-Lin LIU, Jaw-Juinn HORNG, Yung-Chow PENG
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Patent number: 9659919Abstract: In some embodiments, an integrated circuit includes a central array region having a first layout feature density. A background region surrounds the central array region and has a second layout feature density, which is different from the first density. A peripheral array region surrounds the central array region and separates the central array region from the background region. The peripheral array region has a third layout feature density between the first and second layout feature densities.Type: GrantFiled: December 22, 2014Date of Patent: May 23, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Chow Peng, Jaw-Juinn Horng, Szu-Lin Liu, Po-Zeng Kang
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Patent number: 9599517Abstract: A circuit includes sensing circuitry including at least one sensing element configured to output at least one temperature-dependent voltage. A compare circuit is configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage. A control circuit is configured to generate at least one control signal in response to the intermediate voltage. A switching circuit is configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal having a pulse width that is based on a temperature sensed by the sensing circuitry.Type: GrantFiled: October 17, 2013Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Szu-Lin Liu, Jaw-Juinn Horng, Yung-Chow Peng
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Patent number: 9589094Abstract: In some embodiments, a semiconductor device includes a cell array, a first region and a second region. The first region surrounds the cell array and has a first pattern density. The second region is between the cell array and the first region. The second region surrounds the cell array and has a second pattern density smaller than a third pattern density of the cell array, which in turn is smaller than the first pattern density.Type: GrantFiled: May 27, 2015Date of Patent: March 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Szu-Lin Liu, Jaw-Juinn Horng
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Patent number: 9536876Abstract: A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET.Type: GrantFiled: August 1, 2013Date of Patent: January 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yung-Chow Peng, Amit Kundu, Szu-Lin Liu, Jaw-Juinn Horng
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Publication number: 20160373104Abstract: A circuit is disclosed that includes a first differential input pair and a second differential input pair. The first differential input pair is activated according to an output of the second differential input pair, and receives a first temperature-dependent voltage and an output signal. The second differential input pair is activated according to an output of the first differential input pair, and receives a second temperature-dependent voltage and the output signal. The switching circuit couples a capacitive element to a first voltage supply according to the output of the first differential input pair, and the capacitive element to a second voltage supply according to the output of the second differential input pair, to generate the output signal.Type: ApplicationFiled: November 19, 2015Publication date: December 22, 2016Inventors: Jaw-Juinn HORNG, Szu-Lin LIU
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Publication number: 20160292339Abstract: In some embodiments, a semiconductor device includes a cell array, a first region and a second region. The first region surrounds the cell array and has a first pattern density. The second region is between the cell array and the first region. The second region surrounds the cell array and has a second pattern density smaller than a third pattern density of the cell array, which in turn is smaller than the first pattern density.Type: ApplicationFiled: May 27, 2015Publication date: October 6, 2016Inventors: SZU-LIN LIU, JAW-JUINN HORNG
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Publication number: 20160290873Abstract: A temperature sensor arrangement in an integrated circuit (IC) includes a sensor array configured to determine a temperature of the IC. The sensor array includes a first transistor having a first terminal, a second terminal and a gate. The temperature sensor array further includes a guard ring region between the sensor array and another circuit of the IC. The guard ring region includes a transistor structure having a first terminal, a second terminal and a gate. The temperature sensor arrangement further includes a thermally conductive element connected to the transistor structure and a first terminal of the first transistor. The thermally conductive element is configured to provide a thermally conductive path from the transistor structure to the first terminal of the first transistor.Type: ApplicationFiled: May 15, 2015Publication date: October 6, 2016Inventors: Jaw-Juinn HORNG, Szu-Lin LIU
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Patent number: 9354124Abstract: A circuit includes a comparator unit, a capacitive device, and a switching network. The comparator unit is configured to set a control signal at a first logical value when an output voltage reaches a first voltage value from being less than the first voltage value, and to set the control signal at a second logical value when the output voltage reaches a second voltage value from being greater than the second voltage. The capacitive device provides the output voltage. The switching network is configured to charge or discharge the capacitive device based on the control signal.Type: GrantFiled: February 28, 2014Date of Patent: May 31, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jaw-Juinn Horng, Szu-Lin Liu, Chung-Hui Chen
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Publication number: 20160146881Abstract: Some embodiments of the present disclosure provide a method including turning on a noise-measuring system for a device under test (DUT) with the DUT turned off; measuring a first phase noise caused by the noise-measuring system; turning on the DUT; measuring a second phase noise caused by the noise-measuring system and the DUT; and subtracting the first phase noise from the second phase noise to obtain a third phase noise caused by the DUT.Type: ApplicationFiled: May 18, 2015Publication date: May 26, 2016Inventors: JAW-JUINN HORNG, SZU-LIN LIU, JINN-YEH CHIEN
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Publication number: 20150370937Abstract: A method comprises constructing thermal block representations of one or more circuit components or one or more sub-components of the one or more circuit components in an integrated circuit based, at least in part, on defined component parameters. The component parameters describe the one or more sub-components of the one or more circuit components. The thermal block representations have at least one simulation node. The method also comprises supplying a current using at least one current source or voltage controlled current source in a performance simulation. The current is supplied to a thermal path between a first simulation node and a second simulation node. The method further comprises determining a temperature distribution between the first simulation node and the second simulation node based on the current, a first determined voltage at the first simulation node, and a second determined voltage at the second simulation node.Type: ApplicationFiled: June 18, 2014Publication date: December 24, 2015Inventors: Sa-Lly LIU, Szu-Lin LIU, Jaw-Juinn HORNG, Fu-Lung HSUEH
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Publication number: 20150110158Abstract: A circuit includes sensing circuitry including at least one sensing element configured to output at least one temperature-dependent voltage. A compare circuit is configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage. A control circuit is configured to generate at least one control signal in response to the intermediate voltage. A switching circuit is configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal having a pulse width that is based on a temperature sensed by the sensing circuitry.Type: ApplicationFiled: October 17, 2013Publication date: April 23, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Lin LIU, Jaw-Juinn HORNG, Yung-Chow PENG
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Publication number: 20150108610Abstract: In some embodiments, an integrated circuit includes a central array region having a first layout feature density. A background region surrounds the central array region and has a second layout feature density, which is different from the first density. A peripheral array region surrounds the central array region and separates the central array region from the background region. The peripheral array region has a third layout feature density between the first and second layout feature densities.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Inventors: Yung-Chow Peng, Jaw-Juinn Horng, Szu-Lin Liu, Po-Zeng Kang
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Publication number: 20150035568Abstract: A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET.Type: ApplicationFiled: August 1, 2013Publication date: February 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: YUNG-CHOW PENG, AMIT KUNDU, SZU-LIN LIU, JAW-JUINN HORNG