Patents by Inventor Szu-Lin LIU
Szu-Lin LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210091071Abstract: A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.Type: ApplicationFiled: December 4, 2020Publication date: March 25, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Lin LIU, Jaw-Juinn HORNG
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Publication number: 20210090937Abstract: A system for designing a temperature sensor arrangement includes a processor and a non-transitory computer readable medium, including instructions, connected to the processor. The processor is configured to execute the instructions for designing a sensor array, the sensor array includes a first transistor of a first device, and a plurality of second transistors of a second device. The processor is configured to execute the instructions for designing a guard ring region between the sensor array and another circuit of an integrated circuit, the guard ring region includes a transistor structure. The processor is configured to execute the instructions for designing a thermally conductive element between the sensor array and the guard ring region, the thermally conductive element is connected to the transistor structure, the first transistor and each of the plurality of second transistors. The processor is configured to execute the instructions for generating the temperature sensor arrangement.Type: ApplicationFiled: November 17, 2020Publication date: March 25, 2021Inventors: Jaw-Juinn HORNG, Szu-Lin LIU
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Publication number: 20210083129Abstract: A semiconductor device includes a substrate and a plurality of source/drain (S/D) regions in the substrate, wherein each of the plurality of S/D regions includes a first dopant having a first dopant type, and the each of the plurality of S/D regions are electrically coupled together. The semiconductor device further includes a gate stack over the substrate. The semiconductor device further includes a channel region in the substrate, wherein the channel region is below the gate stack and between adjacent S/D regions of the plurality of S/D regions, the channel region includes a second dopant having the first dopant type, and a concentration of the second dopant in the channel region is less than a concentration of the first dopant in each of the plurality of S/D regions.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Inventors: Szu-Lin LIU, Jaw-Juinn HORNG
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Publication number: 20210063254Abstract: A thermal sensor circuit that includes a temperature sensing circuit, an analog to digital converter, a processor, a divider circuit and a digital circuit is introduced. The temperature sensing circuit generates first and second temperature-dependent voltages. The digital to analog converter converts the first and second temperature-dependent voltages to first and second bit streams. The processor generates a third bit stream based on a thermal coefficient. The divider circuit divides one of the first and second bit streams by a denominator value to generate a fourth bit stream, wherein the denominator value is determined according to a bit value of the third bit stream. The digital circuit subtracts the other one of the first and second bit streams from the fourth bit stream to generate an output bit stream. The processor tunes the thermal coefficient until the output bit stream is equivalent to a bit stream of a reference model.Type: ApplicationFiled: May 5, 2020Publication date: March 4, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jaw-Juinn Horng, Szu-Lin Liu
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Patent number: 10883884Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.Type: GrantFiled: April 8, 2019Date of Patent: January 5, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Szu-Lin Liu, Jaw-Juinn Horng, Yung-Chow Peng
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Patent number: 10867109Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling range.Type: GrantFiled: May 29, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsien Yu Tseng, Chun-Wei Chang, Szu-Lin Liu, Amit Kundu, Sheng-Feng Liu
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Patent number: 10861849Abstract: A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.Type: GrantFiled: October 24, 2018Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Szu-Lin Liu, Jaw-Juinn Horng
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Patent number: 10861738Abstract: A method of making a temperature sensor arrangement includes forming a sensor array. The sensor array includes a first transistor of a first device and a plurality of second transistors of a second device different from the first device. The method further includes forming a guard ring region between the sensor array and another circuit of an integrated circuit. The guard ring region includes a transistor structure. The method further includes forming a thermally conductive element between the sensor array and the guard ring region. The thermally conductive element is connected to the transistor structure, the first transistor and each of the plurality of second transistors.Type: GrantFiled: November 30, 2018Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jaw-Juinn Horng, Szu-Lin Liu
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Publication number: 20200116573Abstract: A circuit is disclosed that includes a capacitive element, a control circuit, and a first switch and a second switch. The capacitive element is configured to generate an output voltage at a terminal thereof. The control circuit is configured to generate a first control signal and a second control signal in response to a first temperature-dependent voltage, a second temperature-dependent voltage, and the output voltage. The first switch and the second switch are coupled to the capacitive element, and configured to be turned on or off in response to the first control signal and the second control signal respectively. The first switch and the second switch have different switching status from each other in a charge mode.Type: ApplicationFiled: December 13, 2019Publication date: April 16, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jaw-Juinn HORNG, Szu-Lin LIU
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Publication number: 20200103289Abstract: A thermal sensor in some embodiments comprises two temperature-sensitive branches, each including a thermal-sensing device, such as one or more bipolar-junction transistors, and a current source for generating a current density in the thermal-sensing device to generate a temperature-dependent signal. The thermal sensor further includes a signal processor configured to multiply the temperature-dependent signal from the branches by respective and different gain factors, and combine the resultant signals to generate an output signal that is substantially proportional to the absolute temperature the thermal sensor is disposed at.Type: ApplicationFiled: September 16, 2019Publication date: April 2, 2020Inventors: Jaw-Juinn Horng, Szu-Lin Liu
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Publication number: 20200065451Abstract: An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling range.Type: ApplicationFiled: May 29, 2019Publication date: February 27, 2020Inventors: Hsien YU TSENG, Chun-Wei CHANG, Szu-Lin LIU, Amit KUNDU, Sheng-Feng LIU
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Publication number: 20200058648Abstract: A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.Type: ApplicationFiled: October 24, 2018Publication date: February 20, 2020Inventors: Szu-Lin LIU, Jaw-Juinn HORNG
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Patent number: 10508957Abstract: A circuit is disclosed that includes a first differential input pair, a second differential input pair, and a capacitive element. The first differential input pair is configured to be activated according to an output of the second differential input pair, and the second differential input pair is configured to be activated according to an output of the first differential input pair. The first differential input pair and the second differential input pair each comprises an input configured to receive an output signal. The capacitive element configured to be charged according to the output of the first differential input pair, and configured to be discharged according to the output of the second differential input pair, in order to generate the output signal.Type: GrantFiled: November 20, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jaw-Juinn Horng, Szu-Lin Liu
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Patent number: 10510906Abstract: A metal-oxide-semiconductor (MOS) capacitor is disclosed. The MOS capacitor includes a front-end-of-the-line (FEOL) field effect transistor (FET), and a plurality of middle-end-of-the-line (MEOL) conductive structures. The FEOL FET includes a source region and a drain region positioned in a semiconductor substrate, and a gate over the semiconductor substrate. The plurality of MEOL conductive structures is disposed on a top surface of the gate. At least one of the MEOL conductive structures is electrically disconnected from a back-end-of-the-line (BEOL) metal layer. A semiconductor fabrication method and a MOS capacitor circuit are also disclosed.Type: GrantFiled: July 1, 2016Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Szu-Lin Liu, Jaw-Juinn Horng, Yung-Chow Peng
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Patent number: 10444081Abstract: A circuit includes a first current source that provides a current and a resistive branch in series with the first current source that provides a first voltage value and a second voltage value. A capacitive device is coupled with a voltage node having a voltage value, and a switching network alternates between charging the capacitive device to have the voltage value increase to the first voltage value, and discharging the capacitive device to have the voltage value decrease to the second voltage value.Type: GrantFiled: June 30, 2017Date of Patent: October 15, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jaw-Juinn Horng, Szu-Lin Liu, Chung-Hui Chen
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Publication number: 20190234807Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.Type: ApplicationFiled: April 8, 2019Publication date: August 1, 2019Inventors: Szu-Lin LIU, Jaw-Juinn HORNG, Yung-Chow PENG
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Patent number: 10289777Abstract: A method comprises constructing thermal block representations of one or more circuit components or one or more sub-components of the one or more circuit components in an integrated circuit based, at least in part, on defined component parameters. The component parameters describe the one or more sub-components of the one or more circuit components. The thermal block representations have at least one simulation node. The method also comprises supplying a current using at least one current source or voltage controlled current source in a performance simulation. The current is supplied to a thermal path between a first simulation node and a second simulation node. The method further comprises determining a temperature distribution between the first simulation node and the second simulation node based on the current, a first determined voltage at the first simulation node, and a second determined voltage at the second simulation node.Type: GrantFiled: June 18, 2014Date of Patent: May 14, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sa-Lly Liu, Szu-Lin Liu, Jaw-Juinn Horng, Fu-Lung Hsueh
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Patent number: 10274380Abstract: A three-dimensional integrated circuit includes a first layer including at least one sensing element configured to output at least one temperature-dependent voltage; and a second layer disposed vertically with respect to the first layer and coupled to the first layer by at least one via. The second layer includes: a compare circuit configured to generate at least one intermediate voltage in response to comparing the at least one temperature-dependent voltage to a feedback voltage; a control circuit configured to generate at least one control signal in response to the intermediate voltage; and a switching circuit configured to couple a capacitor coupled to a feedback node to one of a first voltage supply and a second voltage supply in response to the at least one control signal to generate an output signal that is based on a temperature sensed by the sensing element.Type: GrantFiled: March 15, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Szu-Lin Liu, Jaw-Juinn Horng, Yung-Chow Peng
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Publication number: 20190109038Abstract: A method of making a temperature sensor arrangement includes forming a sensor array. The sensor array includes a first transistor of a first device and a plurality of second transistors of a second device different from the first device. The method further includes forming a guard ring region between the sensor array and another circuit of an integrated circuit. The guard ring region includes a transistor structure. The method further includes forming a thermally conductive element between the sensor array and the guard ring region. The thermally conductive element is connected to the transistor structure, the first transistor and each of the plurality of second transistors.Type: ApplicationFiled: November 30, 2018Publication date: April 11, 2019Inventors: Jaw-Juinn HORNG, Szu-Lin LIU
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Patent number: 10163686Abstract: A temperature sensor arrangement in an integrated circuit (IC) includes a sensor array configured to determine a temperature of the IC. The sensor array includes a first transistor having a first terminal, a second terminal and a gate. The temperature sensor array further includes a guard ring region between the sensor array and another circuit of the IC. The guard ring region includes a transistor structure having a first terminal, a second terminal and a gate. The temperature sensor arrangement further includes a thermally conductive element connected to the transistor structure and a first terminal of the first transistor. The thermally conductive element is configured to provide a thermally conductive path from the transistor structure to the first terminal of the first transistor.Type: GrantFiled: May 15, 2015Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jaw-Juinn Horng, Szu-Lin Liu