Abstract: A nonvolatile storage device of an embodiment includes a first wiring layer extending in a first direction, a second wiring layer extending in a second direction intersecting with the first direction, a conductive layer between the first wiring layer and the second wiring layer at an intersection of the first wiring layer and the second wiring layer, and a resistance change region including at least one of an oxide, a nitride, and an oxynitride in the first wiring layer. The resistance change region exists in the first wiring layer including an interface between the first wiring layer and the conductive layer.

Abstract: According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in an interconnect length direction. The device further includes an upper graphene layer formed on an upper face of the catalyst layer, and side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction.

Abstract: According to one embodiment, a semiconductor device includes a first insulating layer on an underlying layer, a first trench formed in the first insulating layer, and a first graphene layer provided in the first trench. The first trench comprises a bottom surface on the underlying and two side surfaces joined to the bottom surface, formed into a U-shape. The first graphene layer has a stacked structure including a plurality of graphene sheets. The plurality of graphene sheets each include a depression in a central portion. Portions of the graphene sheets located in an edge of the first graphene layer are each extended upward, which is in a direction opposite to the bottom surface.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a graphene layer containing impurities, and including a first region and a second region. The second region has a resistance higher than a resistance of the first region. The second region includes a side surface of an end of the graphene layer. The device further includes a first plug being in contact with the first region.

Abstract: According to one embodiment, a semiconductor device includes an n-type semiconductor layer, a first electrode, and a nitride semiconductor layer. The n-type semiconductor layer includes diamond. The nitride semiconductor layer is provided between the n-type semiconductor layer and the first electrode. The nitride semiconductor layer includes AlxGa1?xN (0?x?1) and is of n-type.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.

Abstract: A graphene wring structure of an embodiment includes multilayer graphene, a first interlayer compound existing in an interlayer space of the multilayer graphene, and a second interlayer compound existing in the interlayer space of the multilayer graphene. The second interlayer compound containing at least one of an oxide, a nitride and a carbide.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a graphene film on a catalytic layer, removing a part of the graphene film to form an exposed side surface of the graphene film, introducing dopant into the graphene film from the exposed side surface, and forming a graphene interconnect by patterning the graphene film into which the dopant is introduced.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer thereon. The catalyst layer includes a first to fifth catalyst regions arranged along a first direction in order of the first to fifth catalyst regions. The first, third and fifth catalyst regions include upper surfaces higher than those of the second and fourth catalyst regions. Adjacent ones of the first to fifth catalyst regions are in contact with each other. A distance between the first and the third catalyst region and a distance between the third and fifth catalyst region are greater than a mean free path of graphene. The graphene layer includes a first graphene layer on the second catalyst region and a second graphene layer on the fourth catalyst region.

Abstract: A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.

Abstract: A semiconductor device includes a graphene interconnect, an insulation film formed on the graphene interconnect, and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film. The graphene interconnect has a region containing an impurity at least around the via hole.

Abstract: The sensor includes a first graphene film that is provided on the insulating layer so as to be located in a flow path of a liquid containing the detection target substance, the first graphene film having a first edge that is parallel with a first direction that is along the flow path and a first edge that is parallel with a second direction that is different from the first direction, and the first graphene film having the shape of a band that extends in the second direction. The sensor includes a first electrode that is electrically connected to the first edge of the first graphene film that is parallel with the first direction. The sensor includes a second electrode that is electrically connected to a second edge of the first graphene film that is opposed to the first edge that is parallel with the first direction.

Abstract: A complex marking determining device includes a brightness state calculating portion configured to calculate a lane marking representative value indicative of a brightness state of a plurality of pixels that make up a lane marking display region, and calculate a road surface representative value indicative of a brightness state of a plurality of pixels that make up the road surface display region; and a complex marking determining portion configured to determine that the lane marking is a complex marking at least when a degree of deviation between the lane marking representative value and the road surface representative value is equal to or greater than a first threshold value.

Abstract: A graphene wiring has a substrate, a catalyst layer on the substrate, a graphene layer on the catalyst layer, and a dopant layer on a side surface of the graphene layer. An atomic or molecular species is intercalated in the graphene layer or disposed on the graphene layer.

Abstract: According to one embodiment, a semiconductor device includes an n-type semiconductor layer, a first electrode, and a nitride semiconductor layer. The n-type semiconductor layer includes diamond. The nitride semiconductor layer is provided between the n-type semiconductor layer and the first electrode. The nitride semiconductor layer includes AlxGa1-xN (0?x?1) and is of n-type.

Abstract: A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles.

Abstract: A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer.

Abstract: A semiconductor device of an embodiment includes a p-type first diamond semiconductor layer, a p-type second diamond semiconductor layer disposed on the first diamond semiconductor layer, a plurality of n-type third diamond semiconductor layers disposed on the second diamond semiconductor layer, and a first electrode disposed on the second diamond semiconductor and the third diamond semiconductor layers. The p-type second diamond semiconductor layer has a p-type impurity concentration lower than a p-type impurity concentration of the first diamond semiconductor layer and has oxygen-terminated surfaces. Each of the third diamond semiconductor layers has an oxygen-terminated surface. The first electrode forms first junctions between the first electrode and the second diamond semiconductor. The first electrode forms second junctions between the first electrode and the third diamond semiconductor layers. The first junctions and the second junctions are Schottky junctions.

Abstract: Wiring comprises a multilayer graphene including graphene sheets, an interlayer substance disposed between layers of the multilayer graphene, and an organic compound layer connected to a side surface of the multilayer graphene. The organic compound layer contains a photoisomerizable organic group connected to the multilayer graphene.

Abstract: A carbon nanotube interconnect structure of an embodiment has a first interconnect layer, a first interlayer insulating film on the first interconnect layer, a second interlayer insulating film on the first interlayer insulating film, a contact hole penetrating through the first interlayer insulating film and the second interlayer insulating film, a catalyst metal film on a portion of the first interconnect layer located at a lower end of the contact hole, a second interconnect layer on the second interlayer insulating film, and carbon nanotubes on the catalyst metal film located in the contact hole. The carbon nanotubes electrically connecting the first interconnect layer and the second interconnect layer.