Patents by Inventor Tadashi Sakai

Tadashi Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to produce optical transceiver
    Patent number: 9089084
    Abstract: A method to control an optical transceiver, in particular, to drive an LD installed within the optical transceiver is described. The LD in the bias current thereof is determined by the automatic power control (APC) loop to keep an average of the optical output power. The modulation current is determined by a feedback loop to keep the extinction ratio (ER) in a preset range. The initial condition of the modulation current for the feedback loop is set by T-Im characteristic. The T-Im characteristic is first derived based on data measured in a status of the LD not installed in the transceiver. The T-Im characteristic is revised timely by the modulation current practically obtained for the optical transceiver.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: July 21, 2015
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Toru Ukai, Moriyasu Ichino, Tadashi Sakai
  • CONDUCTIVE FILM AND SEMICONDUCTOR DEVICE
    Publication number: 20150194386
    Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.
    Type: Application
    Filed: March 20, 2015
    Publication date: July 9, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Makoto Wada, Tatsuro Saito, Tadashi Sakai
  • Semiconductor device and method of manufacturing the same
    Patent number: 9076795
    Abstract: According to one embodiment, there is provided a semiconductor device using graphene, includes a catalyst layer formed on or in a substrate along with an interconnect pattern and a graphene layer formed on the catalyst layer. The graphene layer is arranged parallel to a narrower linewidth than the width of the interconnect pattern.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: July 7, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuro Saito, Makoto Wada, Atsunobu Isobayashi, Akihiro Kajita, Tadashi Sakai
  • POLISHING END POINT DETECTION METHOD AND POLISHING END POINT DETECTION APPARATUS
    Publication number: 20150183084
    Abstract: There is provided a polishing end point detection method of improving the accuracy of detecting a polishing end point. The polishing end point detection method emits light toward a polishing object including a hybrid film made of a nanocarbon material and a light-transmissive material while polishing the polishing object (Step S102). Then, the polishing end point detection method receives light reflected from the polishing object (Step S103). Then, the polishing end point detection method subjects the received reflected light to signal processing (Step S104). Then, the polishing end point detection method determines the polishing end point of the polishing object based on the result of the signal processing (Step S105), and detects the polishing end point (Step S106).
    Type: Application
    Filed: December 26, 2014
    Publication date: July 2, 2015
    Inventors: Ban ITO, Naoshi SAKUMA, Akihiro KAJITA, Tadashi SAKAI
  • Semiconductor device and manufacturing method thereof
    Patent number: 9030012
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: May 12, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Akihiro Kajita, Atsunobu Isobayashi, Tatsuro Saito, Tadashi Sakai, Taishi Ishikura
  • Conductive film and semiconductor device
    Patent number: 9000591
    Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Makoto Wada, Tatsuro Saito, Tadashi Sakai
  • SEMICONDUCTOR DEVICE, SUPERCONDUCTING DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    Publication number: 20150080223
    Abstract: A semiconductor device of an embodiment includes a layered substance formed by laminating two-dimensional substances in two or more layers. The layered substance includes at least either one of a p-type region having a first intercalation substance between layers of the layered substance and an n-type region having a second intercalation substance between layers of the layered substance. The layered substance includes a conductive region that is adjacent to at least either one of the p-type region and the n-type region. The conductive region includes neither the first intercalation substance nor the second intercalation substance. A sealing member is formed on the conductive region, or on the conductive region and an end of the layered substance.
    Type: Application
    Filed: September 3, 2014
    Publication date: March 19, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Yuichi Yamazaki, Tadashi Sakai
  • Semiconductor device and method of manufacturing the same
    Patent number: 8981561
    Abstract: According to one embodiment, a semiconductor device in which CNTs are used for a contact via comprise a substrate including a contact via groove, a catalyst layer for CNT growth which is formed at the bottom of the groove, and a CNT via formed by filling the CNTs into the groove in which the catalyst layer is formed. Each of the CNTs is formed by stacking a plurality of graphene layers in a state in which they are inclined depthwise with respect to the groove, and formed such that ends of the graphene layers are exposed on a sidewall of the CNT. Further, the CNT is doped with at least one element from the sidewall of the CNT.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuro Saito, Makoto Wada, Atsunobu Isobayashi, Akihiro Kajita, Hisao Miyazaki, Tadashi Sakai
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150060885
    Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mariko SUZUKI, Tadashi SAKAI, Chiharu OTA, Kazuto TAKAO, Takashi SHINOHE
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    Publication number: 20150061133
    Abstract: According to one embodiment, a semiconductor device using a graphene film comprises a catalytic metal layer formed on a groundwork substrate includes a contact via, and a multilayered graphene layer formed in a direction parallel with a surface of the substrate. The catalytic metal layer is formed to be connected to the contact via and covered with an insulation film except one side surface. The multilayered graphene layer is grown from the side surface of the catalytic metal layer which is not covered with the insulation film.
    Type: Application
    Filed: February 10, 2014
    Publication date: March 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsunobu ISOBAYASHI, Akihiro KAJITA, Tadashi SAKAI
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20150061131
    Abstract: According to one embodiment, a semiconductor device in which CNTs are used for a contact via comprises a substrate includes a contact via groove, a catalyst layer for CNT growth which is formed at the bottom of the groove, and a CNT via formed by filling the CNTs into the groove in which the catalyst layer is formed. Each of the CNTs is formed by stacking a plurality of graphene layers in a state in which they are inclined depthwise with respect to the groove, and formed such that ends of the graphene layers are exposed on a sidewall of the CNT. Further, the CNT is doped with at least one element from the sidewall of the CNT.
    Type: Application
    Filed: March 10, 2014
    Publication date: March 5, 2015
    Inventors: Tatsuro SAITO, Makoto WADA, Atsunobu ISOBAYASHI, Akihiro KAJITA, Hisao MIYAZAKI, Tadashi SAKAI
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150035149
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate provided with a lower interconnect layer formed thereon, and having a device region and a mark formation region, a CNT via structure formed in the device region such that it contacts the lower interconnect layer, a first mark formed in the mark formation region, formed by embedding carbon nanotubes, and formed in the same layer as the CNT via structure, a second mark formed in the mark formation region of the semiconductor substrate, formed with no carbon nanotubes, and formed in the same layer as the CNT via structure and the first mark, and an interconnect layer formed on the CNT via structure and the first and second marks, and electrically connected to the CNT via structure.
    Type: Application
    Filed: January 14, 2014
    Publication date: February 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Makoto WADA, Akihiro KAJITA, Atsunobu ISOBAYASHI, Tatsuro SAITO, Tadashi SAKAI, Taishi ISHIKURA
  • Method of manufacturing interconnection and semiconductor device
    Patent number: 8940628
    Abstract: A method of manufacturing an interconnection of an embodiment includes: forming a via which penetrates an interlayer insulation film on a substrate; forming an underlying film in the via; removing the underlying film on a bottom part of the via; forming a catalyst metal inactivation film on the underlying film; removing the inactivation film on the bottom part of the via; forming a catalyst metal film on the bottom part of the via on which the inactivation film is removed; performing a first plasma treatment and a second plasma treatment using a gas not containing carbon on a member in which the catalyst metal film is formed; forming a graphite layer on the catalyst film after the first and second plasma treatment processes; and causing a growth of a carbon nanotube from the catalyst film on which the graphite layer is formed.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: January 27, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Yamazaki, Tadashi Sakai
  • Semiconductor device and method for manufacturing the same
    Patent number: 8878190
    Abstract: A semiconductor device according to the present embodiment includes a diamond substrate having a surface plane inclined from a (100) plane in a range of 10 degrees to 40 degrees in a direction of <011>±10 degrees, and an n-type diamond semiconductor layer containing phosphorus (P) and formed above the surface plane described above.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Suzuki, Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Yuichi Yamazaki
  • GRAPHENE WIRING
    Publication number: 20140284800
    Abstract: A graphene wiring has a substrate, a catalyst layer on the substrate, a graphene layer on the catalyst layer, and a dopant layer on a side surface of the graphene layer. An atomic or molecular species is intercalated in the graphene layer or disposed on the graphene layer.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi SAKAI, Masayuki KATAGIRI, Yuichi YAMAZAKI, Naoshi SAKUMA, Mariko SUZUKI
  • GRAPHENE WIRING AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20140284798
    Abstract: A graphene wiring has a substrate a catalyst layer on the substrate a first graphene sheet layer on the catalyst layer and a second graphene sheet layer on the first graphene layer. The second graphene layer comprises multilayer graphene sheets. The multilayer graphene sheets are intercalated with an atomic or molecular species.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hisao MIYAZAKI, Tadashi Sakai, Masayuki Katagiri, Yuichi Yamazaki, Mariko Suzuki
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20140284799
    Abstract: A semiconductor device has a substrate a lower layer wiring on the substrate, an interlayer dielectric on the lower layer wiring having a contact hole, a catalyst metal layer at the bottom of the contact hole having catalyst metal particles, multi-walled carbon nanotubes on the catalyst metal layer passing through the contact hole, and an upper layer wiring on the multi-walled carbon nanotubes. The multi-walled carbon nanotubes are intercalated with an atomic or molecular species.
    Type: Application
    Filed: March 10, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masayuki KATAGIRI, Tadashi SAKAI, Hisao MIYAZAKI, Yuichi YAMAZAKI, Mariko SUZUKI
  • SEMICONDUCTOR DEVICE
    Publication number: 20140231751
    Abstract: According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.
    Type: Application
    Filed: August 13, 2013
    Publication date: August 21, 2014
    Inventors: Makoto WADA, Hisao MIYAZAKI, Akihiro KAJITA, Atsunobu ISOBAYASHI, Tatsuro SAITO, Tadashi SAKAI
  • METHOD OF MANUFACTURING INTERCONNECTION AND SEMICONDUCTOR DEVICE
    Publication number: 20140187033
    Abstract: A method of manufacturing an interconnection of an embodiment includes: forming a via which penetrates an interlayer insulation film on a substrate; forming an underlying film in the via; removing the underlying film on a bottom part of the via; forming a catalyst metal inactivation film on the underlying film; removing the inactivation film on the bottom part of the via; forming a catalyst metal film on the bottom part of the via on which the inactivation film is removed; performing a first plasma treatment and a second plasma treatment using a gas not containing carbon on a member in which the catalyst metal film is formed; forming a graphite layer on the catalyst film after the first and second plasma treatment processes; and causing a growth of a carbon nanotube from the catalyst film on which the graphite layer is formed.
    Type: Application
    Filed: December 26, 2013
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuichi YAMAZAKI, Tadashi Sakai
  • SEMICONDUCTOR DEVICE
    Publication number: 20140145210
    Abstract: A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 29, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mariko SUZUKI, Tadashi Sakai, Naoshi Sakuma, Masayuki Katagiri, Yuichi Yamazaki