Abstract: Graphene wiring of an embodiment has a graphene intercalation compound including a multilayer graphene having graphene sheets stacked therein and an interlayer substance disposed between layers of the multilayer graphene, and an interlayer cross-linked layer connected to a side surface of the multilayer graphene. The interlayer cross-linked layer has a cross-linked molecular structure including multiple bonded molecules cross-linking the graphene sheets included in the multilayer graphene.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a first film having a first melting point, forming a pattern of a second film on an upper surface of the first film, the second film having a second melting point lower than the first melting point, and forming a graphene film on the upper surface of the first film, the graphene film being formed from a side surface of the pattern of the second film.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a first interconnect, and an insulating film provided on the first interconnect, and being with a through hole communicating with the first interconnect. A catalyst layer is provided on the first interconnect of a bottom portion of the through hole. The catalyst layer has a form of a continuous film, and includes catalyst material and impurity. A first plug is provided in the through hole and is in contact with the catalyst layer, and includes a carbon nanotube layer. A second interconnect is disposed above the first interconnect and connected to the first interconnect via the first plug.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.

Abstract: According to one embodiment, a semiconductor device using a graphene film comprises a catalytic metal layer formed on a groundwork substrate includes a contact via, and a multilayered graphene layer formed in a direction parallel with a surface of the substrate. The catalytic metal layer is formed to be connected to the contact via and covered with an insulation film except one side surface. The multilayered graphene layer is grown from the side surface of the catalytic metal layer which is not covered with the insulation film.

Abstract: A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer.

Abstract: A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles.

Abstract: A graphene wiring of an embodiment includes graphene, first conductive layers, second conductive layers, and a third conductive layer. The first conductive layers are connected to first sides of the graphene opposite to each other in a longitudinal direction of the wiring. The second conductive layers are connected to second sides of the graphene opposite to each other in a widthwise direction of the wiring. The third conductive layer is connected to a top surface of the graphene. The first and second conductive layers are connected to each other.

Abstract: A graphene wiring of an embodiment includes graphene, first conductive layers, second conductive layers, and a third conductive layer. The first conductive layers are connected to first sides of the graphene opposite to each other in a longitudinal direction of the wiring. The second conductive layers are connected to second sides of the graphene opposite to each other in a widthwise direction of the wiring. The third conductive layer is connected to a top surface of the graphene. The first and second conductive layers are connected to each other.

Abstract: A semiconductor device according to an embodiment includes: a first diamond semiconductor layer of a first conductivity type including a main surface having a first plane orientation; a trench structure formed in the first diamond semiconductor layer; a second diamond semiconductor layer formed on the first diamond semiconductor layer in the trench structure and having a lower dopant concentration than the first diamond semiconductor layer; a third diamond semiconductor layer of a second conductivity type formed on the second diamond semiconductor layer and having a higher dopant concentration than the second diamond semiconductor layer; a first electrode electrically connected to the first diamond semiconductor layer; and a second electrode electrically connected to the third diamond semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes a graphene interconnect, an insulation film formed on the graphene interconnect, and a via conducting portion formed in a via hole provided in the graphene interconnect and the insulation film.

Abstract: A wiring includes a graphene having a five-seven-membered ring-dense region. The graphene has a plurality of unit cells each including a five-seven-membered ring. The length of the unit cell is 1 nm or more. The shortest distance between most closely adjacent unit cells among the unit cells is 5 nm or less in the five-seven-membered ring-dense region.

Abstract: A nonvolatile memory of an embodiment includes first wiring layers of a first conductivity type extending in a first direction, second wiring layers of a second conductivity type extending in a second direction crossing the first direction, memory cells at intersection points of the first and second wiring layers, absorption parts each in contact with peripheral part of each of the memory cells, and an intercalant present in one or both of the memory cell and the absorption part.

Abstract: A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.

Abstract: A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.

Abstract: A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles.

Abstract: According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.

Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.

Abstract: A semiconductor device of an embodiment includes a p-type first diamond semiconductor layer, a p-type second diamond semiconductor layer disposed on the first diamond semiconductor layer, a plurality of n-type third diamond semiconductor layers disposed on the second diamond semiconductor layer, and a first electrode disposed on the second diamond semiconductor and the third diamond semiconductor layers. The p-type second diamond semiconductor layer has a p-type impurity concentration lower than a p-type impurity concentration of the first diamond semiconductor layer and has oxygen-terminated surfaces. Each of the third diamond semiconductor layers has an oxygen-terminated surface. The first electrode forms first junctions between the first electrode and the second diamond semiconductor. The first electrode forms second junctions between the first electrode and the third diamond semiconductor layers. The first junctions and the second junctions are Schottky junctions.

Abstract: According to one embodiment, there is provided a semiconductor device using graphene, includes a catalyst layer formed on or in a substrate along with an interconnect pattern and a graphene layer formed on the catalyst layer. The graphene layer is arranged parallel to a narrower linewidth than the width of the interconnect pattern.