Patents by Inventor Tadatoshi Danno
Tadatoshi Danno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120007224Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.Type: ApplicationFiled: September 22, 2011Publication date: January 12, 2012Applicants: HITACHI HOKKAI SEMICONDUCTOR LTD., RENESAS ELECTRONICS CORPORATIONInventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
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Patent number: 8053875Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.Type: GrantFiled: November 23, 2009Date of Patent: November 8, 2011Assignee: Renesas Electronics CorporationInventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
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Publication number: 20110267790Abstract: The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.Type: ApplicationFiled: July 11, 2011Publication date: November 3, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Tadatoshi DANNO
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Patent number: 8044509Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.Type: GrantFiled: December 30, 2010Date of Patent: October 25, 2011Assignees: Renesas Electronics Corporation, Hitachi Hokkai Semiconductor Ltd.Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
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Publication number: 20110204502Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.Type: ApplicationFiled: May 5, 2011Publication date: August 25, 2011Inventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
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Publication number: 20110198742Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.Type: ApplicationFiled: April 26, 2011Publication date: August 18, 2011Inventors: Tadatoshi Danno, Tsutomu Tsuchiya
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Patent number: 7998796Abstract: The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.Type: GrantFiled: September 13, 2010Date of Patent: August 16, 2011Assignee: Renesas Electronics CorporationInventor: Tadatoshi Danno
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Patent number: 7982301Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.Type: GrantFiled: September 15, 2009Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
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Publication number: 20110121443Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.Type: ApplicationFiled: February 3, 2011Publication date: May 26, 2011Inventors: Tadatoshi DANNO, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
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Patent number: 7937105Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.Type: GrantFiled: February 17, 2008Date of Patent: May 3, 2011Assignee: Renesas Electronics CorporationInventors: Tadatoshi Danno, Tsutomu Tsuchiya
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Publication number: 20110095412Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.Type: ApplicationFiled: December 30, 2010Publication date: April 28, 2011Applicants: RENESAS ELECTRONICS CORPORATION, HITACHI HOKKAI SEMICONDUCTOR, LTD.Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
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Patent number: 7919858Abstract: The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.Type: GrantFiled: April 29, 2009Date of Patent: April 5, 2011Assignee: Renesas Electronics CorporationInventor: Tadatoshi Danno
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Patent number: 7911054Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.Type: GrantFiled: March 25, 2009Date of Patent: March 22, 2011Assignees: Renesas Electronics Corporation, Hitachi Hokkai Semiconductor Ltd.Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
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Publication number: 20100325876Abstract: The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.Type: ApplicationFiled: September 13, 2010Publication date: December 30, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Tadatoshi DANNO
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Patent number: 7833833Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.Type: GrantFiled: November 23, 2009Date of Patent: November 16, 2010Assignee: Renesas Electronics CorporationInventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
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Patent number: 7777309Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.Type: GrantFiled: February 19, 2008Date of Patent: August 17, 2010Assignee: Renesas Technology Corp.Inventors: Tadatoshi Danno, Tsutomu Tsuchiya
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Patent number: 7732910Abstract: In a lead frame, through holes are formed outside suspending leads and trenches are formed on a back surface along the suspending leads so as to communicate with the through holes. When sealing resin is injected into cavities of a resin molding die, air enters the through holes through air vents and flows out from the through holes by a resin injection pressure in the trenches, making it easier for the sealing resin to enter the through holes. Since the sealing resin leaking to the air vents can be injected into the through holes, it is possible to enhance the bonding force between the sealing resin after curing and the lead frame in the vicinity of the air vents and effect release of the resin molding die, while allowing the sealing resin leaking to the air vents to remain on the lead frame side without remaining within the air vents.Type: GrantFiled: April 3, 2007Date of Patent: June 8, 2010Assignee: Renesas Technology Corp.Inventor: Tadatoshi Danno
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Patent number: 7709937Abstract: A semiconductor device which includes: a semiconductor chip with plural pads; a tab connected with the semiconductor chip; bus bars which are located outside of the semiconductor chip and connected with the tab; a sealing body which resin-seals the semiconductor chip; plural leads arranged in a line around the semiconductor chip; plural first wires which connect pads of the semiconductor chip and the leads; and plural second wires which connect specific pads of the semiconductor chip and the bus bars. Since the sealing body has a continuous portion which continues from a side surface of the semiconductor chip to its back surface to a side surface of the tab, the degree of adhesion among the semiconductor chip, the tab and the sealing body is increased. This prevents peeling between the tab and the sealing body during a high-temperature process and thus improves the quality of the semiconductor device (QFN).Type: GrantFiled: September 13, 2007Date of Patent: May 4, 2010Assignee: Renesas Technology Corp.Inventor: Tadatoshi Danno
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Patent number: 7691677Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.Type: GrantFiled: November 24, 2008Date of Patent: April 6, 2010Assignee: Renesas Technology Corp.Inventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
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Publication number: 20100068852Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.Type: ApplicationFiled: November 23, 2009Publication date: March 18, 2010Inventors: Tadatoshi DANNO, Hiroyoshi Taya, Yoshiharu Shimizu