Patents by Inventor Tadatoshi Danno

Tadatoshi Danno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100065951
    Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 18, 2010
    Inventors: Tadatoshi DANNO, Hiroyoshi Taya, Yoshiharu Shimizu
  • Publication number: 20100001393
    Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.
    Type: Application
    Filed: September 15, 2009
    Publication date: January 7, 2010
    Inventors: Tadatoshi DANNO, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
  • Publication number: 20090309210
    Abstract: The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.
    Type: Application
    Filed: April 29, 2009
    Publication date: December 17, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventor: Tadatoshi Danno
  • Patent number: 7608922
    Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: October 27, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Tadatoshi Danno, Toru Nagamine, Hiroshi Mori, Tsukasa Ichinose
  • Publication number: 20090218676
    Abstract: A small-sized surface mount package having a low on-resistance is achieved, in which a power MOSFET etc. is sealed. In one side a molding resin, two silicon chips are sealed. On one side of the molding resin, three source leads and one gate lead are arranged. The three source leads are joined each other inside the molding resin, and the joined portion and a source pad of the silicon chip are electrically coupled each other via two Al ribbons. Moreover, a gate pad of the silicon chip is electrically coupled to the gate lead via one Au wire.
    Type: Application
    Filed: February 25, 2009
    Publication date: September 3, 2009
    Inventors: Kuniharu MUTO, Tadatoshi DANNO, Hiroyuki TAKAHASHI
  • Publication number: 20090189260
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Application
    Filed: March 25, 2009
    Publication date: July 30, 2009
    Applicants: RENESAS TECHNOLOGY CORP., HITACHI HOKKAI SEMICONDUCTOR, LTD.
    Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
  • Patent number: 7518156
    Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: April 14, 2009
    Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor Ltd.
    Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
  • Publication number: 20090075427
    Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.
    Type: Application
    Filed: November 24, 2008
    Publication date: March 19, 2009
    Inventors: Tadatoshi DANNO, Hiroyoshi TAYA, Yoshiharu SHIMIZU
  • Patent number: 7425756
    Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: September 16, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Tadatoshi Danno, Tsutomu Tsuchiya
  • Publication number: 20080146187
    Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.
    Type: Application
    Filed: February 17, 2008
    Publication date: June 19, 2008
    Inventors: Tadatoshi DANNO, Tsutomu Tsuchiya
  • Publication number: 20080135960
    Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.
    Type: Application
    Filed: February 19, 2008
    Publication date: June 12, 2008
    Inventors: Tadatoshi DANNO, Tsutomu Tsuchiya
  • Publication number: 20080012118
    Abstract: A semiconductor device which includes: a semiconductor chip with plural pads; a tab connected with the semiconductor chip; bus bars which are located outside of the semiconductor chip and connected with the tab; a sealing body which resin-seals the semiconductor chip; plural leads arranged in a line around the semiconductor chip; plural first wires which connect pads of the semiconductor chip and the leads; and plural second wires which connect specific pads of the semiconductor chip and the bus bars. Since the sealing body has a continuous portion which continues from a side surface of the semiconductor chip to its back surface to a side surface of the tab, the degree of adhesion among the semiconductor chip, the tab and the sealing body is increased. This prevents peeling between the tab and the sealing body during a high-temperature process and thus improves the quality of the semiconductor device (QFN).
    Type: Application
    Filed: September 13, 2007
    Publication date: January 17, 2008
    Inventor: Tadatoshi DANNO
  • Publication number: 20080006916
    Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.
    Type: Application
    Filed: September 11, 2007
    Publication date: January 10, 2008
    Inventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
  • Patent number: 7312511
    Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: December 25, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tadatoshi Danno, Tsutomu Tsuchiya
  • Patent number: 7285444
    Abstract: A semiconductor device which includes: a semiconductor chip with plural pads; a tab connected with the semiconductor chip; bus bars which are located outside of the semiconductor chip and connected with the tab; a sealing body which resin-seals the semiconductor chip; plural leads arranged in a line around the semiconductor chip; plural first wires which connect pads of the semiconductor chip and the leads; and plural second wires which connect specific pads of the semiconductor chip and the bus bars. Since the sealing body has a continuous portion which continues from a side surface of the semiconductor chip to its back surface to a side surface of the tab, the degree of adhesion among the semiconductor chip, the tab and the sealing body is increased. This prevents peeling between the tab and the sealing body during a high-temperature process and thus improves the quality of the semiconductor device (QFN).
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: October 23, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Tadatoshi Danno
  • Patent number: 7282396
    Abstract: The quality of a non-leaded semiconductor device is to be improved. The semiconductor device comprises a sealing body for sealing a semiconductor chip with resin, a tab disposed in the interior of the sealing body, suspension leads for supporting the tab, plural leads having respective to-be-connected surfaces exposed to outer edge portions of a back surface of the sealing body, and plural wires for connecting pads formed on the semiconductor chip and the leads with each other. End portions of the suspending leads positioned in an outer periphery portion of the sealing body are not exposed to the back surface of the sealing body, but are covered with the sealing body. Therefore, stand-off portions of the suspending leads are not formed in resin molding.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: October 16, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
  • Publication number: 20070181985
    Abstract: In a lead frame, through holes are formed outside suspending leads and trenches are formed on a back surface along the suspending leads so as to communicate with the through holes. When sealing resin is injected into cavities of a resin molding die, air enters the through holes through air vents and flows out from the through holes by a resin injection pressure in the trenches, making it easier for the sealing resin to enter the through holes. Since the sealing resin leaking to the air vents can be injected into the through holes, it is possible to enhance the bonding force between the sealing resin after curing and the lead frame in the vicinity of the air vents and effect release of the resin molding die, while allowing the sealing resin leaking to the air vents to remain on the lead frame side without remaining within the air vents.
    Type: Application
    Filed: April 3, 2007
    Publication date: August 9, 2007
    Inventor: Tadatoshi Danno
  • Publication number: 20070126083
    Abstract: The semiconductor device provided assures stable communication processes. For example, a varactor diode for adjusting the reference frequency is comprised within a digital crystal-controlled oscillating circuit provided as an internal circuit of the front-end circuit for generating the reference oscillation signal of a PLL circuit or the like. The varactor diode is formed to a semiconductor layer DF of the so-called SOI structure in the structure where an embedded insulating layer, a n?type semiconductor region, a p type semiconductor region, and a n+ type semiconductor region are formed in this sequence and the n+ type semiconductor region is connected to a cathode node which becomes the frequency adjusting node. Moreover, a p+ type semiconductor region connected to the p type semiconductor region is formed in both sides of the n+ type semiconductor region, and this p+ type semiconductor region is connected to an anode node to which the ground voltage is applied.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 7, 2007
    Inventors: Kentaro SUZUKI, Ikuya Ono, Tadatoshi Danno
  • Patent number: 7220607
    Abstract: In a lead frame, through holes are formed outside suspending leads and trenches are formed on a back surface along the suspending leads so as to communicate with the through holes. When sealing resin is injected into cavities of a resin molding die, air enters the through holes through air vents and flows out from the through holes by a resin injection pressure in the trenches, making it easier for the sealing resin to enter the through holes. Since the sealing resin leaking to the air vents can be injected into the through holes, it is possible to enhance the bonding force between the sealing resin after curing and the lead frame in the vicinity of the air vents and effect release of the resin molding die, while allowing the sealing resin leaking to the air vents to remain on the lead frame side without remaining within the air vents.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: May 22, 2007
    Assignee: Renesas Technology Corp.
    Inventor: Tadatoshi Danno
  • Publication number: 20060237830
    Abstract: This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconductor device includes a sealing body which is made of insulation resin, a plurality of leads which are provided inside and outside the sealing body, a tab which is provided inside the sealing body and has a semiconductor element fixing region and a wire connection region on a main surface thereof, a semiconductor element which is fixed to the semiconductor element fixing region and includes electrode terminals on an exposed main surface, conductive wires which connect electrode terminals of the semiconductor element and the leads, and conductive wires which connect electrode terminals of the semiconductor element and the wire connecting region of the tab.
    Type: Application
    Filed: June 19, 2006
    Publication date: October 26, 2006
    Inventors: Tadatoshi Danno, Tsutomu Tsuchiya