Patents by Inventor Takamasa Usui
Takamasa Usui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240038731Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: ApplicationFiled: October 13, 2023Publication date: February 1, 2024Applicant: KIOXIA CORPORATIONInventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
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Patent number: 11817428Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: GrantFiled: February 1, 2022Date of Patent: November 14, 2023Assignee: KIOXIA CORPORATIONInventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
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Publication number: 20220157784Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Applicant: KIOXIA CORPORATIONInventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
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Patent number: 11270980Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: GrantFiled: June 30, 2020Date of Patent: March 8, 2022Assignee: KIOXIA CORPORATIONInventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
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Patent number: 10879137Abstract: According to an embodiment, a template includes a flat plate-shaped first member, a flat plate-shaped second member including a pattern arrangement face, and a flat plate-shaped third member provided with an opening at a position corresponding to an arrangement position of the second member. The template is dividable at a position of at least one of a first boundary between the first member and the second member and a second boundary between the first member and the third member.Type: GrantFiled: February 21, 2018Date of Patent: December 29, 2020Assignee: Toshiba Memory CorporationInventors: Takahito Nishimura, Suigen Kanda, Takamasa Usui, Masayoshi Tagami, Jun Iljima
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Patent number: 10868029Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.Type: GrantFiled: September 11, 2018Date of Patent: December 15, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Jun Iijima, Masayoshi Tagami, Takamasa Usui, Takahito Nishimura
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Publication number: 20200350291Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: ApplicationFiled: June 30, 2020Publication date: November 5, 2020Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
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Patent number: 10741527Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: GrantFiled: April 22, 2019Date of Patent: August 11, 2020Assignee: Toshiba Memory CorporationInventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
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Publication number: 20190312012Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: ApplicationFiled: April 22, 2019Publication date: October 10, 2019Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Ryota KATSUMATA, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Genki FUJITA
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Publication number: 20190296035Abstract: According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.Type: ApplicationFiled: September 11, 2018Publication date: September 26, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Jun IIJIMA, Masayoshi Tagami, Takamasa Usui, Takahito Nishimura
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Patent number: 10297578Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: GrantFiled: September 15, 2017Date of Patent: May 21, 2019Assignee: Toshiba Memory CorporationInventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
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Publication number: 20190074230Abstract: According to an embodiment, a template includes a flat plate-shaped first member, a flat plate-shaped second member including a pattern arrangement face, and a flat plate-shaped third member provided with an opening at a position corresponding to an arrangement position of the second member. The template is dividable at a position of at least one of a first boundary between the first member and the second member and a second boundary between the first member and the third member.Type: ApplicationFiled: February 21, 2018Publication date: March 7, 2019Applicant: Toshiba Memory CorporationInventors: Takahito NISHIMURA, Suigen KANDA, Takamasa USUI, Masayoshi TAGAMI, Jun llJIMA
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Publication number: 20180261575Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.Type: ApplicationFiled: September 15, 2017Publication date: September 13, 2018Applicant: Toshiba Memory CorporationInventors: Masayoshi TAGAMI, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
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Patent number: 9887262Abstract: A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion. The device includes a first interconnection provided on a first portion and a second interconnection provided on the second portion. The first interconnection and the second interconnection extend in a first direction. The device further includes a conductor and a nitride layer. The conductor extends through the first insulating film in a second direction from each of the first interconnection and the second interconnection toward the semiconductor layer, and the conductor electrically connects the first interconnection to the semiconductor layer. The nitrided layer is provided at least on the third surface.Type: GrantFiled: August 27, 2015Date of Patent: February 6, 2018Assignee: Toshiba Memory CorporationInventors: Yoshihiro Minami, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Masayoshi Tagami
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Patent number: 9589974Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.Type: GrantFiled: January 24, 2014Date of Patent: March 7, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Jun Iijima, Yoshiaki Himeno, Takamasa Usui
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Patent number: 9504127Abstract: Illumination apparatus management system includes a plurality of illumination apparatuses, and server. Each of the plurality of illumination apparatuses transmits a status of use of illumination apparatus to server. Server includes: communication unit that obtains the status of use of the illumination apparatus transmitted by each of the plurality of illumination apparatuses, and obtains a requirement from a user; and selector that selects illumination apparatus matching the obtained requirement from among the plurality of illumination apparatuses based on the obtained status of use, and outputs a selection result indicating illumination apparatus that has been selected.Type: GrantFiled: May 29, 2015Date of Patent: November 22, 2016Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventor: Takamasa Usui
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Patent number: 9466779Abstract: A piezoelectric actuator includes one piezoelectric layer, a common electrode disposed on the lower surface of the piezoelectric layer and individual electrodes disposed on the upper surface of the piezoelectric layer. In the piezoelectric layer, a plurality of metal patterns arranged at regular intervals in the conveyance direction and in a direction orthogonal to the conveyance direction and overlapping with pressure chambers are provided substantially at the central part in the direction of the thickness. The metal patterns are not electrically continuous with each other and not electrically continuous with other parts. The metal patterns situated outermost in the conveyance direction are disposed so as to cross the edge of the pressure chamber. Some metal patterns overlap with the individual electrode and the other metal patterns do not overlap with the individual electrode.Type: GrantFiled: July 15, 2014Date of Patent: October 11, 2016Assignee: BROTHER KOGYO KABUSHIKI KAISHAInventors: Takamasa Usui, Yasuhiro Sekiguchi, Tomohiro Nodsu
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Publication number: 20160247783Abstract: A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion. The device includes a first interconnection provided on a first portion and a second interconnection provided on the second portion. The first interconnection and the second interconnection extend in a first direction. The device further includes a conductor and a nitride layer. The conductor extends through the first insulating film in a second direction from each of the first interconnection and the second interconnection toward the semiconductor layer, and the conductor electrically connects the first interconnection to the semiconductor layer. The nitrided layer is provided at least on the third surface.Type: ApplicationFiled: August 27, 2015Publication date: August 25, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Yoshihiro MINAMI, Jun IIJIMA, Tetsuya SHIMIZU, Takamasa USUI, Masayoshi TAGAMI
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Publication number: 20150351196Abstract: Illumination apparatus management system includes a plurality of illumination apparatuses, and server. Each of the plurality of illumination apparatuses transmits a status of use of illumination apparatus to server. Server includes: communication unit that obtains the status of use of the illumination apparatus transmitted by each of the plurality of illumination apparatuses, and obtains a requirement from a user; and selector that selects illumination apparatus matching the obtained requirement from among the plurality of illumination apparatuses based on the obtained status of use, and outputs a selection result indicating illumination apparatus that has been selected.Type: ApplicationFiled: May 29, 2015Publication date: December 3, 2015Inventor: Takamasa USUI
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Patent number: 9196609Abstract: A semiconductor device includes a first contact plug, a diametric dimension of an upper end portion thereof greater than the lower end portion thereof; a first insulating film above a substrate and covering the first plug; a second contact plug, a diametric dimension of an upper end portion thereof less than lower end portion thereof, the lower end portion contacting the upper end portion of the first plug; a second insulating film above the first insulating film and the first plug and covering the second plug; a wiring layer including a lower end portion contacting the upper end portion of the second plug; and a third insulating film above the second insulating film and the second plug and covering the wiring layer; wherein the upper end portion of the first plug displaced from the lower end portion of the second plug has a step.Type: GrantFiled: March 13, 2014Date of Patent: November 24, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hajime Kaneko, Keiichi Shimada, Takamasa Usui