Patents by Inventor Takamasa Usui

Takamasa Usui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7936070
    Abstract: A semiconductor device includes: a copper (Cu) wire having a first region and a second region in which densities of silicon (Si) and oxygen (O) atoms are higher than in the first region; a compound film that is selectively formed on the Cu wire and contains Cu and Si; and a dielectric film formed on a side surface side of the Cu wire.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: May 3, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Hayashi, Noriaki Matsunaga, Takamasa Usui
  • Publication number: 20110097890
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted meta
    Type: Application
    Filed: January 3, 2011
    Publication date: April 28, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takamasa USUI, Tadayoshi WATANABE, Hayato NASU
  • Patent number: 7922282
    Abstract: A cap apparatus includes a cap which seals nozzles of a liquid jetting head, an absorber which is accommodated tightly inside the cap, a cap holder which is accommodated tightly inside the cap, and a holder which has a holding body which makes a contact with an upper surface of the absorber, a pin which is protruded downward from the holding main portion, and an engaging portion which is provided on a front end of the pin. Through holes which make the cap, the absorber, and the cap holder communicate, are formed in the cap, the absorber, and the cap holder. Since the through holes function as a passage, it is possible to improve an assembling workability of the cap apparatus.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: April 12, 2011
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Tatsuya Shindo, Takamasa Usui
  • Publication number: 20110074885
    Abstract: A droplet ejecting apparatus, including: a head having a cavity unit with pressure chambers and a piezoelectric actuator; and a voltage application device, the actuator including: first and second active portions; a first potential electrode; a second potential electrode including a second trunk portion; and individual electrodes each having a connection portion, wherein the connection portion is disposed to overlap the second trunk portion as seen in a superposition direction of the cavity unit and the actuator, wherein the individual electrodes are arranged in rows to correspond to rows of the pressure chambers, and all connecting portions belonging to any one row are disposed on the same side in a direction of arrangement of the rows, and wherein the connecting portions of the individual electrodes that belong to one and the other of any adjacent two rows are disposed on mutually opposite sides with respect to the corresponding pressure chambers.
    Type: Application
    Filed: March 29, 2010
    Publication date: March 31, 2011
    Inventors: Takamasa Usui, Yasuhiro Sekiguchi, Yoshitsugu Morita
  • Patent number: 7898084
    Abstract: A semiconductor device is disclosed, which includes a first interlayer insulating film, a lower-layer interconnection in a first groove in the first film, a second interlayer insulating film over the first film, having a normal via hole opening to the lower-layer interconnection, a normal plug in the normal hole, a third interlayer insulating film over the second film, having a second groove opening to the normal plug, an upper-layer interconnection in the second groove, and a first dummy plug in a first dummy via hole in the second film, the first dummy via hole opening to one of the lower-layer and upper-layer interconnections, wherein a short side of the first dummy plug is larger than a minimum width of a minimum width interconnection and smaller than a minimum diameter of a minimum diameter via hole and a long side is larger than a shortest length of a shortest length interconnection.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: March 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayo Kobayashi, Takamasa Usui
  • Patent number: 7888253
    Abstract: A method of fabricating a semiconductor device according to an embodiment includes: forming a precursor film containing therein a predetermined metallic element on a surface of a recess portion formed in an insulating film on a semiconductor substrate; forming a wiring formation film on the precursor film; performing a heat treatment in an oxidation ambient atmosphere to cause the precursor film and the insulating film to react with each other, thereby forming a self-formed barrier film containing a compound, containing therein the predetermined metallic element and a constituent element of the insulating film, as a basic constituent in a boundary surface between the precursor film and the insulating film, and moving the predetermined metallic element unreacted into the wiring formation film through diffusion to cause the predetermined metallic element unreacted to react with oxygen contained in the oxidation ambient atmosphere on a surface of the wiring formation film, thereby precipitating an unreacted meta
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takamasa Usui, Tadayoshi Watanabe, Hayato Nasu
  • Patent number: 7875976
    Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a silicide layer provided on the semiconductor substrate, a dielectric layer provided on the semiconductor substrate, a contact layer provided on the silicide layer, a metal layer provided in the dielectric layer and electrically connected to the silicide layer via the contact layer, a diffusion barrier layer provided between the dielectric layer and the metal layer, wherein the contact layer includes a first metal element provided in the metal layer, a second metal element provided in the diffusion barrier layer and at least one of a third metal provided in the silicide layer and Si element.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: January 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Wada, Takamasa Usui, Kazuya Ohuchi
  • Patent number: 7847405
    Abstract: In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench, the first barrier layer being an oxide film made from a metal different from a main constituent metal element in the wiring layer, a second barrier layer formed on a side surface of the wiring layer, the second barrier layer having a Si atom of the metal used in the wiring layer, and a gap formed between the first barrier layer and the second barrier layer.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: December 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadayoshi Watanabe, Yumi Hayashi, Takamasa Usui
  • Patent number: 7810899
    Abstract: An inkjet printer has a printing head having a nozzle surface on which a plurality of nozzles are located that spray a plurality of kinds of ink and a cap that covers the nozzle surface of the printing head. This cap includes a ring-shaped seal lip that is constructed so that the tip end thereof comes in contact with the nozzle surface to perform capping and a partitioning lip that partitions the area inside the seal lip into areas for nozzle groups that correspond to the kinds of ink. The tip end of either seal lip or partitioning lip is shaped so that it is compressed more easily than that of the other.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: October 12, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Takamasa Usui, Katsunori Nishida
  • Publication number: 20100244254
    Abstract: A semiconductor device is disclosed, which includes a first interlayer insulating film, a lower-layer interconnection in a first groove in the first film, a second interlayer insulating film over the first film, having a normal via hole opening to the lower-layer interconnection, a normal plug in the normal hole, a third interlayer insulating film over the second film, having a second groove opening to the normal plug, an upper-layer interconnection in the second groove, and a first dummy plug in a first dummy via hole in the second film, the first dummy via hole opening to one of the lower-layer and upper-layer interconnections, wherein a short side of the first dummy plug is larger than a minimum width of a minimum width interconnection and smaller than a minimum diameter of a minimum diameter via hole and a long side is larger than a shortest length of a shortest length interconnection.
    Type: Application
    Filed: March 24, 2010
    Publication date: September 30, 2010
    Inventors: Takayo Kobayashi, Takamasa Usui
  • Publication number: 20100223768
    Abstract: There is provided a method of manufacturing liquid transporting apparatus including: providing a channel unit; providing a piezoelectric actuator having a first and second active portion corresponding to a central portion and an outer periphery portion of the pressure chamber, respectively. The first and second active portions are sandwiched between an upper electrode and an intermediate electrode, and between the upper electrode and a lower electrode, respectively. The method further includes joining the channel unit and the piezoelectric actuator by positioning such that the intermediate electrode overlaps the central portion of the pressure chamber. Accordingly, since it is possible to make the first active portion overlap the central portion of the pressure chamber, it is possible to apply a appropriate pressure to the liquid in the pressure chamber without excessively small deformation of the first active portion.
    Type: Application
    Filed: March 5, 2010
    Publication date: September 9, 2010
    Inventors: Yasuhiro SEKIGUCHI, Takamasa Usui
  • Patent number: 7786523
    Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: August 31, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Hayashi, Hayato Nasu, Kazumichi Tsumura, Takamasa Usui, Hiroyoshi Tanimoto
  • Patent number: 7780260
    Abstract: An inkjet printer includes a recording head having a nozzle face provided with a nozzle for discharging an ink to form an image on a recording medium, and a detachable cap for capping the nozzle face. The cap of the inkjet printer is provided with an annular rim and an annular groove, which are provided along a periphery of the cap, the groove being opposed to the nozzle face in a state where the cap is abutted against the nozzle face. In the inkjet printer, a during non-image-forming period, the rim of the cap is abutted against the nozzle face, thus capping the nozzle face.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 24, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Takamasa Usui
  • Patent number: 7755202
    Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate having a semiconductor element formed on a surface thereof; an interwiring insulating film formed above the semiconductor substrate; a wiring formed in the interwiring insulating film; a first intervia insulating film formed under the interwiring insulating film; a first via formed in the first intervia insulating film and connected to a lower surface of the wiring; a second intervia insulating film formed on the interwiring insulating film; a second via formed in the second intervia insulating film and connected to an upper surface of the wiring; and a CuSiN film formed in at least one of a position between the interwiring insulating film and the first intervia insulating film, and a position between the interwiring insulating film and the second intervia insulating film.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: July 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Hayashi, Tadayoshi Watanabe, Takamasa Usui
  • Patent number: 7750473
    Abstract: Provided is a semiconductor device including first and second wiring layers, and dummy and conductive patterns. The first and second wiring layers each have a hollow structure, and are stacked vertically adjacent to each other on a semiconductor substrate. The dummy pattern is formed in the first wiring layer, and does not function as a signal line. The conductive pattern is formed in the second wiring layer. The dummy and conductive patterns have an overlapping portion where these patterns overlap each other, and a non-overlapping portion where these patterns overlap each other, as viewed from above the semiconductor substrate.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takamasa Usui, Hideki Shibata, Tadashi Murofushi, Masakazu Jimbo, Hiroshi Hirayama
  • Patent number: 7735956
    Abstract: A recovery device comprising: a cap configured to cover a nozzle face in which a plurality of nozzle groups are formed; and a cap holder supporting the cap; wherein the cap includes: a sealing lip being configured to sealingly contact the nozzle face; a plurality of partitioning lips that partition an inside area surrounded by the sealing lip into a plurality of compartments corresponding to the respective nozzle groups; and a plurality of suction openings provided in the respective compartments; and wherein a common flow path, which is communicated with suction openings of some or all compartments and connects the suction openings to a negative pressure source, is formed in the cap or in the cap holder, or by a space containing faces of the cap and the cap holder opposed to each other.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: June 15, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Takamasa Usui, Katsunori Nishida
  • Publication number: 20100052028
    Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.
    Type: Application
    Filed: November 16, 2009
    Publication date: March 4, 2010
    Inventors: Yumi HAYASHI, Hayato Nasu, Kazumichi Tsumura, Takamasa Usui, Hiroyoshi Tanimoto
  • Patent number: 7661805
    Abstract: An ink-jet printer including: a buffer tank; an air-discharging valve device; and a valve opening-and-closing device. The ink-jet printer further includes an operating member which is arranged to be interposed between the air-discharging valve device and the valve opening-and-closing device. The valve opening-and-closing device operates the air-discharging valve device via the operating member, such that the air-discharging valve device is placed in a valve-open state and a valve-close state. The ink-jet printer is arranged to execute a first discharge operation in which the air separated from the ink in the buffer tank is discharged while placing the air-discharging valve device in the valve open state, and a second discharge operation in which an inside of the air-discharging valve device is exhausted to remove the ink remaining in the air-discharging valve device while placing the air-discharging valve device in the valve-close state.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: February 16, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Takamasa Usui
  • Patent number: 7651184
    Abstract: A liquid droplet ejecting apparatus comprises an ejecting head including a passage which is connected to a sub-tank and an ejecting pressure applying device which applies a feed pressure to the liquid inside the passage, a main tank detector which detects that a main tank is mounted to a main tank mounting portion, a suction pump which applies a negative pressure to an air layer inside the sub-tank to discharge air from inside the sub-tank to outside, and a controller configured to control the suction pump and the ejecting pressure applying device, based on information from the main tank detector. The controller causes the suction pump to discharge the air from inside the sub-tank to outside and causes the ejecting pressure applying device to eject the liquid from a nozzle, when the main tank detector detects that the main tank is mounted to the main tank mounting portion.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: January 26, 2010
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Hirotake Nakamura, Takamasa Usui, Naoya Okazaki
  • Patent number: 7638829
    Abstract: A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: December 29, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yumi Hayashi, Hayato Nasu, Kazumichi Tsumura, Takamasa Usui, Hiroyoshi Tanimoto