Patents by Inventor Takamasa Usui

Takamasa Usui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150076708
    Abstract: A semiconductor device includes a first contact plug, a diametric dimension of an upper end portion thereof greater than the lower end portion thereof; a first insulating film above a substrate and covering the first plug; a second contact plug, a diametric dimension of an upper end portion thereof less than lower end portion thereof, the lower end portion contacting the upper end portion of the first plug; a second insulating film above the first insulating film and the first plug and covering the second plug; a wiring layer including a lower end portion contacting the upper end portion of the second plug; and a third insulating film above the second insulating film and the second plug and covering the wiring layer; wherein the upper end portion of the first plug displaced from the lower end portion of the second plug has a step.
    Type: Application
    Filed: March 13, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hajime KANEKO, Keiichi Shimada, Takamasa Usui
  • Publication number: 20150069491
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.
    Type: Application
    Filed: January 24, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jun IIJIMA, Yoshiaki HIMENO, Takamasa USUI
  • Patent number: 8959733
    Abstract: There is provided a method of manufacturing liquid transporting apparatus including: providing a channel unit; providing a piezoelectric actuator having a first and second active portion corresponding to a central portion and an outer periphery portion of the pressure chamber, respectively. The first and second active portions are sandwiched between an upper electrode and an intermediate electrode, and between the upper electrode and a lower electrode, respectively. The method further includes joining the channel unit and the piezoelectric actuator by positioning such that the intermediate electrode overlaps the central portion of the pressure chamber. Accordingly, since it is possible to make the first active portion overlap the central portion of the pressure chamber, it is possible to apply a appropriate pressure to the liquid in the pressure chamber without excessively small deformation of the first active portion.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: February 24, 2015
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Yasuhiro Sekiguchi, Takamasa Usui
  • Publication number: 20150048721
    Abstract: A piezoelectric actuator includes one piezoelectric layer, a common electrode disposed on the lower surface of the piezoelectric layer and individual electrodes disposed on the upper surface of the piezoelectric layer. In the piezoelectric layer, a plurality of metal patterns arranged at regular intervals in the conveyance direction and in a direction orthogonal to the conveyance direction and overlapping with pressure chambers are provided substantially at the central part in the direction of the thickness. The metal patterns are not electrically continuous with each other and not electrically continuous with other parts. The metal patterns situated outermost in the conveyance direction are disposed so as to cross the edge of the pressure chamber. Some metal patterns overlap with the individual electrode and the other metal patterns do not overlap with the individual electrode.
    Type: Application
    Filed: July 15, 2014
    Publication date: February 19, 2015
    Inventors: Takamasa USUI, Yasuhiro Sekiguchi, Tomohiro Nodsu
  • Patent number: 8772942
    Abstract: A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: July 8, 2014
    Assignees: International Business Machines Corporation, Toshiba America Electronic Components, Inc.
    Inventors: Daniel C. Edelstein, Takeshi Nogami, Kazumichi Tsumura, Takamasa Usui
  • Patent number: 8716134
    Abstract: A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: May 6, 2014
    Assignees: International Business Machines Corporation, Toshiba America Electronic Components, Inc.
    Inventors: Daniel C. Edelstein, Takeshi Nogami, Kazumichi Tsumura, Takamasa Usui
  • Patent number: 8474953
    Abstract: A droplet ejecting apparatus, including: a head having a cavity unit with pressure chambers and a piezoelectric actuator; and a voltage application device, the actuator including: first and second active portions; a first potential electrode; a second potential electrode including a second trunk portion; and individual electrodes each having a connection portion, wherein the connection portion is disposed to overlap the second trunk portion as seen in a superposition direction of the cavity unit and the actuator, wherein the individual electrodes are arranged in rows to correspond to rows of the pressure chambers, and all connecting portions belonging to any one row are disposed on the same side in a direction of arrangement of the rows, and wherein the connecting portions of the individual electrodes that belong to one and the other of any adjacent two rows are disposed on mutually opposite sides with respect to the corresponding pressure chambers.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: July 2, 2013
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Takamasa Usui, Yasuhiro Sekiguchi, Yoshitsugu Morita
  • Patent number: 8456186
    Abstract: A reliability evaluation test apparatus of this invention includes a wafer storage section which stores a wafer in a state wherein the electrode pads of a number of devices formed on the wafer and the bumps of a contactor are totally in electrical contact with each other. The wafer storage section transmits/receives a test signal to/from a measurement section and has a hermetic and heat insulating structure. The wafer storage section has a pressure mechanism which presses the contactor and a heating mechanism which directly heats the wafer totally in contact with the contactor to a predetermined high temperature. The reliability of an interconnection film and insulating film formed on the semiconductor wafer are evaluated under an accelerated condition.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: June 4, 2013
    Assignees: Tokyo Electron Limited, Ibiden Co., Ltd.
    Inventors: Kiyoshi Takekoshi, Hisatomi Hosaka, Junichi Hagihara, Kunihiko Hatsushika, Takamasa Usui, Hisashi Kaneko, Nobuo Hayasaka, Yoshiyuki Ido
  • Patent number: 8454135
    Abstract: An ink jet printer including a carriage which is movable relative to a sheet of paper, a recording head which is mounted on the carriage and records an image on the sheet by ejecting a droplet of ink toward the sheet, one or more ink tanks which store the ink or inks to be supplied to the recording head, a buffer tank which is mounted on the carriage, and one or more ink flow passages in which the inks are supplied from the ink tanks to the recording head via the buffer tank. The buffer tank has, at a height position higher than a height position where the recording head is provided, one or more air buffer chambers which accommodate respective amounts of the inks, and collect air bubbles produced in the ink flow passages.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: June 4, 2013
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Takaichiro Umeda, Hikaru Kaga, Tsuyoshi Suzuki, Seiji Shimizu, Takamasa Usui, Yoichiro Shimizu
  • Patent number: 8377822
    Abstract: A semiconductor structure having a cap layer formed over a metalized dielectric layer is formed by depositing manganese on the surface of the metalized dielectric layer. The deposited manganese serves as a first cap layer to remove oxidation on the surface of the metalized dielectric layer. The presence of oxidation on the surface of the metalized dielectric layer can be delirious for performance of a device constructed out of the semiconductor structure. A second cap layer is then formed by depositing silicon carbide or nitrogen enriched silicon carbide over the first cap layer.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: February 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumichi Tsumura, Takamasa Usui
  • Patent number: 8133813
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: March 13, 2012
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Publication number: 20110285024
    Abstract: A semiconductor structure having a cap layer formed over a metalized dielectric layer is formed by depositing manganese on the surface of the metalized dielectric layer. The deposited manganese serves as a first cap layer to remove oxidation on the surface of the metalized dielectric layer. The presence of oxidation on the surface of the metalized dielectric layer can be delirious for performance of a device constructed out of the semiconductor structure. A second cap layer is then formed by depositing silicon carbide or nitrogen enriched silicon carbide over the first cap layer.
    Type: Application
    Filed: May 21, 2010
    Publication date: November 24, 2011
    Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventors: Kazumichi Tsumura, Takamasa Usui
  • Patent number: 8044519
    Abstract: A method of fabricating a semiconductor device includes forming an insulating film above a semiconductor substrate, forming a concave portion in the insulating film, forming a precursor film including a predetermined metallic element on a surface of the insulating film, carrying out a heat treatment on the precursor film and the insulating film to react with each other, thereby forming an insulative barrier film mainly comprising a compound of the predetermined metallic element and a constituent element of the insulating film in a self-aligned manner at a boundary surface between the precursor film and the insulating film, removing an unreacted part of the precursor film after forming the barrier film, forming a conductive film comprising at least one of Ru and Co on the barrier film, depositing a wiring material film on the conductive film, and forming a wiring from the wiring material film to provide a wiring structure.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadayoshi Watanabe, Takamasa Usui
  • Patent number: 8029115
    Abstract: A liquid ejection device of a first aspect of the invention includes a sub tank capable of fluid communicating with the main tank removably mountable to the liquid ejection device. The sub tank is configured to satisfy the formula: SH?SL?MH?MN where SH is a liquid amount in the sub tank in a balanced state at which the liquid has flowed into the sub tank by a hydraulic head pressure on mounting the main tank with the liquid fully filled; SL is a liquid amount in the sub tank in a state where the liquid level is positioned at the outlet of the sub tank; MH is a liquid amount in the main tank when the liquid is fully filled in the main tank; and MN is a liquid amount in the main tank in a state where the liquid level is positioned at a threshold level.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: October 4, 2011
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Takamasa Usui
  • Patent number: 8020981
    Abstract: There is provides an inkjet recording apparatus comprising: an inkjet head held in a head holder; and an ink tank mounted on the head holder. The ink tank has an ink chamber, a path for communicating the chamber with atmosphere, and an exit valve to open and close the path. The apparatus further comprises: an ink cartridge arranged below the ink tank for supplying the ink to the ink chamber through a channel; an operating member for opening and closing the exit valve; a ink transfer device; and a controller. The controller performs controls of causing the operating member to open the exit valve such that an atmosphere pressure affects an inside of the ink chamber, and such that the ink both in the chamber and in the channel returns to the ink cartridge through the channel; and causing the device to fill the chamber.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: September 20, 2011
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Hisaki Sakurai, Takamasa Usui
  • Publication number: 20110189849
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Application
    Filed: April 14, 2011
    Publication date: August 4, 2011
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Junichi KOIKE, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Publication number: 20110189850
    Abstract: A first insulating film is formed on a semiconductor substrate. A first interconnection is formed in a trench formed in the first insulating film. A first barrier film is formed between the first interconnection and first insulating film. A second insulating film is formed on the upper surface of the first interconnection, and in a first hollow portion between the side surface of the first barrier film and the first insulating film. The second insulating film is formed from the upper surface of the first interconnection to a depth higher than the bottom surface of the first interconnection. The first hollow portion is formed below the bottom surface of the second insulating film.
    Type: Application
    Filed: April 12, 2011
    Publication date: August 4, 2011
    Inventors: Takamasa USUI, Tadayoshi WATANABE
  • Publication number: 20110180309
    Abstract: A metallic liner stack including at least a Group VIIIB element layer and a CuMn alloy layer is deposited within a trench in a dielectric layer. Copper is deposited on the metallic liner stack and planarized to form a conductive interconnect structure, which can be a metal line, a metal via, or a combination thereof. The deposited copper and the metallic liner stack are annealed before or after planarization. The Mn atoms are gettered by the Group VIIIB element layer to form a metallic alloy liner including Mn and at least one of Group VIIIB elements. Mn within the metallic alloy liner combines with oxygen during the anneal to form MnO, which acts as a strong barrier to oxygen diffusion, thereby enhancing the reliability of the conductive interconnect structure.
    Type: Application
    Filed: January 26, 2010
    Publication date: July 28, 2011
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
    Inventors: Daniel C. Edelstein, Takeshi Nogami, Kazumichi Tsumura, Takamasa Usui
  • Patent number: 7943517
    Abstract: A method of manufacturing a semiconductor device, including forming an opening in an interlevel insulating film disposed on a semiconductor substrate, forming an auxiliary film containing a predetermined metal element, to cover an inner surface of the opening, forming a main film to fill the opening after forming the auxiliary film, the main film containing, as a main component, Cu used as a material of an interconnection main layer, and performing a heat treatment before or after forming the main film, thereby diffusing the predetermined metal element of the auxiliary film onto a surface of the interlevel insulating film facing the auxiliary film, so as to form a barrier film on the interlevel insulating film within the opening, the barrier film containing, as a main component, a compound of the predetermined metal element with a component element of the interlevel insulating film.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: May 17, 2011
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Junichi Koike, Makoto Wada, Shingo Takahashi, Noriyoshi Shimizu, Hideki Shibata, Satoshi Nishikawa, Takamasa Usui, Hayato Nasu, Masaki Yoshimaru
  • Patent number: 7944053
    Abstract: A first insulating film is formed on a semiconductor substrate. A first interconnection is formed in a trench formed in the first insulating film. A first barrier film is formed between the first interconnection and first insulating film. A second insulating film is formed on the upper surface of the first interconnection, and in a first hollow portion between the side surface of the first barrier film and the first insulating film. The second insulating film is formed from the upper surface of the first interconnection to a depth higher than the bottom surface of the first interconnection. The first hollow portion is formed below the bottom surface of the second insulating film.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: May 17, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takamasa Usui, Tadayoshi Watanabe