Patents by Inventor Takashi Hirao
Takashi Hirao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10884030Abstract: In an object of the present invention, an object is to provide a technique for achieving higher accuracy in current detection of a radio frequency current, in a current detection device. The current detection device of the present invention includes two or more conductors through which a current shunted from a same conductor flows; conductors through which the shunted current flows have portions opposed to each other; currents flow in opposite directions in opposing portions of the conductors; and a magnetic field detecting element is provided between the opposing portions of the conductors.Type: GrantFiled: December 4, 2017Date of Patent: January 5, 2021Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventors: Takashi Hirao, Akihiro Namba
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Publication number: 20200258853Abstract: A power conversion device includes first and second power semiconductor elements, and a circuit for transferring a drive signal of the first and second power semiconductor elements. The circuit board includes a first emitter wire which is formed along an arranging direction of the first power semiconductor element and the second power semiconductor element, a first gate wire which is disposed between the first power semiconductor element and the first emitter wire, a second gate wire which is disposed between the second power semiconductor element and the emitter wire, a third gate wire which is disposed to face the first gate wire and the second gate wire with the emitter wire interposed between the third gate wire and the first gate wire and the second gate wire, and a first gate resistor which connects the first gate wire and the third gate wire over the first emitter wire.Type: ApplicationFiled: July 27, 2018Publication date: August 13, 2020Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.Inventors: Akihiro NAMBA, Takashi HIRAO, Masami OONISHI
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Publication number: 20200227333Abstract: An object of the present invention is to provide a power semiconductor device enabling maintenance in reliability and improvement in productivity. According to the present invention, provided are: a circuit body including a semiconductor element and a conductive portion; a first insulation and a second insulation opposed to each other, the circuit body being interposed between the first insulation and the second insulation; a first base and a second base opposed to each other, the circuit body, the first insulation, and the second insulation being interposed between the first base and the second base; a case having a first opening portion covered with the first base and a second opening portion covered with the second base; and a distance regulation portion provided in space between the first base and the second base, the distance regulation portion regulating a distance between the first base and the second base in contact with the first base and the second base.Type: ApplicationFiled: May 22, 2018Publication date: July 16, 2020Inventors: Nobutake TSUYUNO, Hiromi SHIMAZU, Akihiro NAMBA, Akira MATSUSHITA, Hiroshi HOUZOUJI, Atsuo NISHIHARA, Toshiaki ISHII, Takashi HIRAO
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Publication number: 20190271724Abstract: In an object of the present invention, an object is to provide a technique for achieving higher accuracy in current detection of a radio frequency current, in a current detection device. The current detection device of the present invention includes two or more conductors through which a current shunted from a same conductor flows; conductors through which the shunted current flows have portions opposed to each other; currents flow in opposite directions in opposing portions of the conductors; and a magnetic field detecting element is provided between the opposing portions of the conductors.Type: ApplicationFiled: December 4, 2017Publication date: September 5, 2019Applicant: Hitachi Automotive Systems, Ltd.Inventors: Takashi HIRAO, Akihiro NAMBA
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Publication number: 20190229032Abstract: To improve yield and reliability at the time when a plurality of semiconductor elements used for a semiconductor device is arranged in parallel.Type: ApplicationFiled: July 19, 2017Publication date: July 25, 2019Inventors: Masami OONISHI, Takashi HIRAO
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Publication number: 20190146018Abstract: The present invention aims to reduce the leakage current that flows when measuring a high voltage and includes: a voltage detector that detects a voltage and outputs a detection voltage; a current supplier that supplies a measurement current across a pair of input terminals via a protective resistor; and a processor that executes a voltage measurement process, which measures the voltage based on data indicating the detection voltage, and a resistance measurement process, which measures a resistance connected between the input terminals based on the voltage and the current. A first switch is connected in parallel to the protective resistor and the processor executes the voltage measurement process in a state where the first switch has been set open to measure the terminal voltage, and executes the resistance measurement process by setting the first switch shorted when the voltage is equal to or below the reference voltage value.Type: ApplicationFiled: January 11, 2019Publication date: May 16, 2019Applicant: HIOKI DENKI KABUSHIKI KAISHAInventors: Tetsuya NAKAMURA, Takashi HIRAO, Yuta AKAMATSU, Yuta SUZUKI
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Patent number: 10109549Abstract: In order to improve productivity of a semiconductor device, while improving stability of the blocking voltage of the semiconductor device, this semiconductor device is characterized by having a semiconductor element, and a laminated structure having three resin layers, said laminated structure being in a peripheral section surrounding a main electrode on one surface of the semiconductor element. The semiconductor device is also characterized in that the laminated structure has, on the center section side of the semiconductor element, a region where a lower resin layer is in contact with an intermediate resin layer, and a region where the lower resin layer is in contact with an upper resin layer.Type: GrantFiled: December 24, 2014Date of Patent: October 23, 2018Assignee: Hitachi, Ltd.Inventors: Takashi Hirao, Kan Yasui, Kazuhiro Suzuki
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Publication number: 20180267715Abstract: According to one embodiment, the memory system includes a nonvolatile memory including a plurality of blocks, and a controller circuit that controls execution of a data writing process and a garbage collection process. Each of the blocks is an unit of erasure. The data writing process includes a process of writing user data into the nonvolatile memory in accordance with a request from an external member. The garbage collection process includes a process of moving valid data in at least a first block into a second block among the blocks and invalidating the valid data in the first block to be erasable. Upon receiving a data write request from the external member, the controller circuit controls a length of a waiting time to be provided before or after the data writing process within a period from receiving the write request to returning a response to the external member.Type: ApplicationFiled: March 8, 2018Publication date: September 20, 2018Applicant: Toshiba Memory CorporationInventors: Hiroki Matsudaira, Norio Aoyama, Ryoichi Kato, Taku Ooneda, Takashi Hirao, Aurelien Nam Phong Tran, Hiroyuki Yamaguchi, Takuya Suzuki, Hajime Yamazaki
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Publication number: 20170352604Abstract: In order to improve productivity of a semiconductor device, while improving stability of the blocking voltage of the semiconductor device, this semiconductor device is characterized by having a semiconductor element, and a laminated structure having three resin layers, said laminated structure being in a peripheral section surrounding a main electrode on one surface of the semiconductor element. The semiconductor device is also characterized in that the laminated structure has, on the center section side of the semiconductor element, a region where a lower resin layer is in contact with an intermediate resin layer, and a region where the lower resin layer is in contact with an upper resin layer.Type: ApplicationFiled: December 24, 2014Publication date: December 7, 2017Applicant: Hitachi, Ltd.Inventors: Takashi HIRAO, Kan YASUI, Kazuhiro SUZUKI
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Patent number: 9711590Abstract: There is provided a semiconductor device including corundum crystal films of good quality. There is provided a semiconductor device including a base substrate, a semiconductor layer, and an insulating film each having a corundum crystal structure. Materials having a corundum crystal structure include many types of oxide films capable of functioning as an insulating film. Since all the base substrate, the semiconductor layer, and the insulating film have a corundum crystal structure, it is possible to achieve a semiconductor layer and an insulating film of good quality on the base substrate.Type: GrantFiled: September 24, 2013Date of Patent: July 18, 2017Assignee: FLOSFIA, INC.Inventors: Kentaro Kaneko, Toshimi Hitora, Takashi Hirao
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Patent number: 9654027Abstract: A semiconductor device is provided that can prevent a current from being concentrated into a specific chip, and can reduce loss as well as noise. The semiconductor device according to the present invention includes: a switching element; a main diode that is connected in parallel to the switching element; and an auxiliary diode that is connected in parallel to the switching element and has a different structure from that of the main diode, wherein in a conductive state a current flowing through the auxiliary diode is smaller than that through the main diode, and in a transition period from the conductive state to a non-conductive state a current flowing through the auxiliary diode is larger than that through the main diode.Type: GrantFiled: May 22, 2015Date of Patent: May 16, 2017Assignee: Hitachi, Ltd.Inventors: Takashi Hirao, Mutsuhiro Mori
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Patent number: 9304906Abstract: According to one embodiment, a memory system includes non-volatile memory, a block management table that stores whether data in the non-volatile memory is valid or invalid in a unit of cluster, and a controller configured to execute compaction. In the block management table, first information related to likelihood that valid data within the block is invalidated is registered for each of the blocks. The controller is configured to select a block to be a target of the compaction based on the first information and use the selected block to execute the compaction.Type: GrantFiled: March 7, 2014Date of Patent: April 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroki Matsudaira, Takashi Hirao, Aurelien Nam Phong Tran
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Patent number: 9251055Abstract: A memory system in embodiments includes a nonvolatile semiconductor memory that stores user data, a forward lookup address translation table and a reverse lookup address translation table, and a controller. The controller is configured to determine that the user data stored in the nonvolatile semiconductor memory is valid or invalid based on these two tables. The controller may perform data organizing of selecting data determined valid and rewriting the data in a new block. The controller may perform write processing and rewriting processing to the new block alternately at a predetermined ratio. The controller may determine whether a predetermined condition is satisfied on a basis of addresses included in write requests and write data in the MLC mode when the condition is satisfied and write data in the SLC mode when the condition is not satisfied.Type: GrantFiled: August 30, 2012Date of Patent: February 2, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Yonezawa, Takashi Hirao, Hirokuni Yano, Mitsunori Tadokoro, Hiroki Matsudaira, Akira Sawaoka
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Publication number: 20150340965Abstract: A semiconductor device is provided that can prevent a current from being concentrated into a specific chip, and can reduce loss as well as noise. The semiconductor device according to the present invention includes: a switching element; a main diode that is connected in parallel to the switching element; and an auxiliary diode that is connected in parallel to the switching element and has a different structure from that of the main diode, wherein in a conductive state a current flowing through the auxiliary diode is smaller than that through the main diode, and in a transition period from the conductive state to a non-conductive state a current flowing through the auxiliary diode is larger than that through the main diode.Type: ApplicationFiled: May 22, 2015Publication date: November 26, 2015Inventors: Takashi HIRAO, Mutsuhiro MORI
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Publication number: 20150194479Abstract: There is provided a semiconductor device including corundum crystal films of good quality. There is provided a semiconductor device including a base substrate, a semiconductor layer, and an insulating film each having a corundum crystal structure. Materials having a corundum crystal structure include many types of oxide films capable of functioning as an insulating film. Since all the base substrate, the semiconductor layer, and the insulating film have a corundum crystal structure, it is possible to achieve a semiconductor layer and an insulating film of good quality on the base substrate.Type: ApplicationFiled: September 24, 2013Publication date: July 9, 2015Applicant: FLOSFIA INC.Inventors: Kentaro Kaneko, Toshimi Hitora, Takashi Hirao
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Publication number: 20150074335Abstract: According to one embodiment, a memory system includes non-volatile memory, a block management table that stores whether data in the non-volatile memory is valid or invalid in a unit of cluster, and a controller configured to execute compaction. In the block management table, first information related to likelihood that valid data within the block is invalidated is registered for each of the blocks. The controller is configured to select a block to be a target of the compaction based on the first information and use the selected block to execute the compaction.Type: ApplicationFiled: March 7, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hiroki MATSUDAIRA, Takashi Hirao, Aurelien Nam Phong Tran
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Patent number: 8924636Abstract: A management information generating method wherein logical and physical block addresses (BAs) of continuous addresses are associated with each other in the BA translation table. When a logical block is constructed, a value is set for a maximum number of allowable defective physical blocks. A logical block having fewer defects than the set number is set usable, and a logical block having more defects than the set number is set unusable. System logical block construction is performed to preferentially select physical blocks from a plane list including a large number of usable blocks to equalize the number of usable blocks in each plane list. It is determined whether the number of free blocks is insufficient on the basis of a first management unit and whether the storage area for the indicated capacity can be reserved on the basis of the management unit different from the first unit.Type: GrantFiled: September 11, 2012Date of Patent: December 30, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Hirao, Hirokuni Yano, Aurelien Nam Phong Tran, Mitsunori Tadokoro, Hiroki Matsudaira, Tatsuya Sumiyoshi, Yoshimi Niisato, Kenji Tanaka
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Patent number: 8901838Abstract: The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.Type: GrantFiled: July 27, 2012Date of Patent: December 2, 2014Assignee: Renesas Electronics CorporationInventors: Noboru Akiyama, Takayuki Hashimoto, Takashi Hirao, Nobuyoshi Matsuura, Hideo Ishii
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Patent number: 8825946Abstract: According to one embodiment, when a controller writes update data in a second memory to a first memory which is nonvolatile and a difference between a size of a page and a size of the update data is equal to or greater than a size of a cluster, the controller configured to generate write data by adding, to the update data, data which has the size of the cluster, store an update content of management information corresponding to the update data and an update content storage position indicating a storage position of the update content of the management information in the first memory, and write the generated write data to a block in writing of the first memory.Type: GrantFiled: September 14, 2012Date of Patent: September 2, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Ryoichi Kato, Mitsunori Tadokoro, Takashi Hirao
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Patent number: 8745443Abstract: According to one embodiment, a memory system includes a data manager and a data restorer. The data manager multiplexes difference logs by a parallel writing operation and stores them in a second storage area, the difference logs being difference logs indicating difference information before and after update of a management table; and thereafter multiplexes predetermined data as finalizing logs and stores them in the second storage area. The data restorer determines a system status at startup of the memory system, by judging whether irregular power-off occurs or data destruction occurs in the second storage area, based on a data storage state of the difference logs and the finalizing logs stored in the second storage area.Type: GrantFiled: December 15, 2011Date of Patent: June 3, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Hirao, Mitsunori Tadokoro, Hirokuni Yano