Patents by Inventor Takashi Kuroi
Takashi Kuroi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8592284Abstract: Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.Type: GrantFiled: June 30, 2009Date of Patent: November 26, 2013Assignee: Renesas Electronics CorporationInventors: Masato Ishibashi, Katsuyuki Horita, Tomohiro Yamashita, Takaaki Tsunomura, Takashi Kuroi
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Patent number: 8043918Abstract: To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating filType: GrantFiled: July 21, 2010Date of Patent: October 25, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Kuroi, Katsuyuki Horita, Masashi Kitazawa, Masato Ishibashi
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Publication number: 20100285651Abstract: To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating filType: ApplicationFiled: July 21, 2010Publication date: November 11, 2010Applicant: Renesas Technology Corp.Inventors: Takashi KUROI, Katsuyuki HORITA, Masashi KITAZAWA, Masato ISHIBASHI
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Patent number: 7791163Abstract: In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.Type: GrantFiled: October 18, 2005Date of Patent: September 7, 2010Assignee: Renesas Technology Corp.Inventors: Takashi Kuroi, Katsuyuki Horita, Masashi Kitazawa, Masato Ishibashi
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Publication number: 20100044802Abstract: Provided are a semiconductor device making it possible to form an element region having a dimension close to a designed dimension, restrain a phenomenon similar to gate-induced drain leakage, and further restrain compressive stress to be applied to the element region by oxidation of a conductive film; and a method for manufacturing the semiconductor device. Trenches are made in a main surface of a semiconductor substrate. By oxidizing the wall surface of each of the trenches, a first oxide film is formed on the wall surface. An embedded conductive film is formed to be embedded into the trench. The embedded conductive film is oxidized in an atmosphere containing an active oxidizing species, thereby forming a second oxide film. A third oxide film is formed on the second oxide film by CVD or coating method.Type: ApplicationFiled: June 30, 2009Publication date: February 25, 2010Inventors: Masato Ishibashi, Katsuyuki Horita, Tomohiro Yamashita, Takaaki Tsunomura, Takashi Kuroi
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Publication number: 20070241373Abstract: In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.Type: ApplicationFiled: October 18, 2005Publication date: October 18, 2007Applicant: Renesas Technology Corp.Inventors: Takashi Kuroi, Katsuyuki Horita, Masashi Kitazawa, Masato Ishibashi
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Publication number: 20060163624Abstract: The present invention provides a semiconductor device having a fully silicided gate electrode (full-silicide gate electrode) and a manufacturing method thereof, that has no problem of the increase in junction leak current, can increase a thickness of a metal silicide film formed on a source/drain region, and can form a fully silicided gate electrode and metal silicide film with one silicide forming process. A metal silicide film is formed such that its upper main face becomes higher than a semiconductor substrate. The thickness of the metal silicide film can be increased in order to secure a sufficient distance from an interface between the metal silicide film and the semiconductor substrate to an interface between a source/drain diffusion layer and the semiconductor substrate. As a result, the thickness of the metal silicide layer can be increased while avoiding the increase in junction leak current, even if a full-silicide gate electrode is formed.Type: ApplicationFiled: December 29, 2005Publication date: July 27, 2006Applicant: Renesas Technology Corp.Inventor: Takashi Kuroi
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Publication number: 20060027883Abstract: An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method.Type: ApplicationFiled: October 4, 2005Publication date: February 9, 2006Applicant: Renesas Technology Corp.Inventors: Takashi Kuroi, Yasuyoshi Itoh, Katsuyuki Horita, Katsuomi Shiozawa
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Patent number: 6890837Abstract: A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.Type: GrantFiled: October 14, 2003Date of Patent: May 10, 2005Assignee: Renesas Technology Corp.Inventors: Takashi Kuroi, Katsuyuki Horita, Katsuomi Shiozawa
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Patent number: 6841440Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.Type: GrantFiled: January 28, 2003Date of Patent: January 11, 2005Assignee: Renesas Technology Corp.Inventors: Takashi Kuroi, Syuichi Ueno, Katsuyuki Horita
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Publication number: 20040159857Abstract: A semiconductor device is provided which can avoid electrical short circuits between contact plugs, connected to gate electrodes, and source/drain regions. Portions of a polysilicon film (7) that are covered by photoresist (8) are left nonetched to form plate-like polysilicon films (10). The polysilicon films (10) are formed on a first portion of an element isolation insulating film (2). The polysilicon films (10) are connected to polysilicon films (9). Contact plugs (24) are formed on the polysilicon films (10). This prevents electrical short circuits between the contact plugs (24) and drain and source regions (5) and (6).Type: ApplicationFiled: October 21, 2003Publication date: August 19, 2004Applicant: Renesas Technology Corp.Inventors: Katsuyuki Horita, Takashi Kuroi, Masashi Kitazawa
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Publication number: 20040124491Abstract: A high impurity concentration region (31) that an impurity concentration is higher than that of a center part of a channel region (24) is placed in parts which intersect a Y direction in a side surface (14T) of an active region (14). Furthermore, a low impurity concentration region (32) that an impurity concentration is lower than that of the high impurity concentration region (31) is placed in parts which intersect an X direction in the side surface (14T). A source/drain region (231) overlaps with the low impurity concentration region (32), and in that overlapped part, the formation of a high concentration PN junction is suppressed.Type: ApplicationFiled: June 3, 2003Publication date: July 1, 2004Applicant: Renesas Technology Corp.Inventors: Tomohiro Yamashita, Katsuyuki Horita, Takashi Kuroi
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Publication number: 20040108524Abstract: In an isolation structure formed by filling an isolation film (2) in a trench (12) formed in the surface of a substrate (1), the isolation film (2) contains an impurity whose concentration decreases from the bottom portion to top portion of the isolation film (2).Type: ApplicationFiled: June 4, 2003Publication date: June 10, 2004Applicant: Renesas Technology Corp.Inventors: Masashi Kitazawa, Takashi Kuroi
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Patent number: 6744113Abstract: In a trench (2), an oxynitride film (31ON1) and a silicon oxide film (31O1) are positioned between a doped silicon oxide film (31D) and a substrate (1), and a silicon oxide film (31O2) is positioned closer to the entrance of the trench (2) than the doped silicon oxide film (31D). The oxynitride film (31ON1) is formed by a nitridation process utilizing the silicon oxide film (31O1). The vicinity of the entrance of the trench (2) is occupied by the silicon oxide films (31O1, 31O2) and the oxynitride film (31ON1).Type: GrantFiled: March 4, 2003Date of Patent: June 1, 2004Assignee: Renesas Technology Corp.Inventors: Takashi Kuroi, Tomohiro Yamashita, Katsuyuki Horita
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Patent number: 6737315Abstract: A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.Type: GrantFiled: August 6, 2002Date of Patent: May 18, 2004Assignee: Renesas Technology Corp.Inventors: Takashi Kuroi, Katsuyuki Horita, Katsuomi Shiozawa
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Publication number: 20040092057Abstract: An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method.Type: ApplicationFiled: October 31, 2003Publication date: May 13, 2004Applicant: MITSUBISHI DENKI KABUSHIKIInventors: Takashi Kuroi, Yasuyoshi Itoh, Katsuyuki Horita, Katsuomi Shiozawa
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Publication number: 20040082165Abstract: A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.Type: ApplicationFiled: October 14, 2003Publication date: April 29, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takashi Kuroi, Katsuyuki Horita, Katsuomi Shiozawa
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Publication number: 20040053458Abstract: In a trench (2), an oxynitride film (31ON1) and a silicon oxide film (31O1) are positioned between a doped silicon oxide film (31D) and a substrate (1), and a silicon oxide film (31O2) is positioned closer to the entrance of the trench (2) than the doped silicon oxide film (31D). The oxynitride film (31ON1) is formed by a nitridation process utilizing the silicon oxide film (31O1). The vicinity of the entrance of the trench (2) is occupied by the silicon oxide films (31O1, 31O2) and the oxynitride film (31ON1).Type: ApplicationFiled: March 4, 2003Publication date: March 18, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takashi Kuroi, Tomohiro Yamashita, Katsuyuki Horita
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Patent number: 6707099Abstract: A semiconductor device less susceptible to inverse narrow channel effect and its manufacturing method are provided. A silicon nitride film (13) is adopted as element isolation regions; the silicon nitride film (13) has a smaller etch rate than a sacrificial silicon oxide film (7) which serves as a sacrificial layer during ion implantation (8). This prevents formation of recesses in the silicon nitride film (13) during the removal of the sacrificial silicon oxide film (7), which weakens the strength of the electric fields at the gate edges. Weakening the strength of the electric fields at the gate edges suppresses the inverse narrow channel effect, so that the MOS transistor offers a characteristic closer to a characteristic in which the threshold voltage keeps a constant value independently of the channel width. Thus an MOS transistor having a good characteristic can be manufactured.Type: GrantFiled: August 15, 2002Date of Patent: March 16, 2004Assignee: Renesas Technology Corp.Inventors: Katsuomi Shiozawa, Takashi Kuroi, Katsuyuki Horita
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Patent number: 6667221Abstract: A technique for preventing a decrease in alignment accuracy during a photolithography process is provided. A substrate (1) is prepared, in the surface (80) of which trenches (7) for use as alignment marks and trenches (17, 27) each forming an element isolation structure are formed and on the surface (80) of which a polysilicon film (3) is formed, avoiding the trenches (7, 17, 27). The trenches (7, 17, 27) are filled with an insulation film (30). The insulation film (30) is then selectively etched to partially remove the insulation film (30) in the trenches (7) and to leave the insulation film (30) on side and bottom surfaces (81, 82) of the trenches (7). Using the insulation film (30) in the trenches (7) as a protective film, the polysilicon film (3) is selectively etched. The use of the insulation film (30) in the trenches (7) as a protective film prevents the substrate (1) from being etched and thereby prevents the shape of the trenches (7) from being changed.Type: GrantFiled: August 6, 2002Date of Patent: December 23, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Masashi Kitazawa, Tomohiro Yamashita, Takashi Kuroi