Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.

Abstract: Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region (1) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region (22) including a channel region. In the channel dope region (1), it is set so that the maximum value of the P type impurity concentration (MAX of P) ranges from 1×1018 to 1×1019, and the maximum value of the N type impurity concentration (MAX of N) of a source/drain region (31 (32)) is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region (22) is to be beyond the object.

Abstract: A trench is formed in a silicon substrate (1) and an oxide film (11) is provided on an inner wall of the trench. The trench is filled with an oxide film (7) through the oxide film (11). A gate oxide film (14) is formed on the silicon substrate (1). A bottom of a recess F2, defined by the gate oxide film (14) and the oxide films (11, 17), is arranged in a position more approximated to the oxide film (7) for filling the trench than a boundary between the silicon substrate (1) and the oxide film (11). A concentration of a field from a gate electrode (16) is suppressed in the vicinity of the element isolation.

Abstract: An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method.

Abstract: Provided are a semiconductor device that can obtain more output current without increasing the occupied area of a MOS transistor, and a method for manufacturing the same. MOS transistors (M11, M12) are electrically isolated by a trench isolation oxide film (21). The MOS transistor (M11) has a groove portion (GP) in which the width of the top is 20 nm to 80 nm and the depth is 50 nm to 150 nm. The groove portion (GP) is disposed at the boundary part between a trench isolation insulating film (22) and an active region (AR1) so as to surround the active region (AR1). A gate electrode (31A) is not only disposed above the active region (AR1) but also buried in the groove (GP) with a gate oxide film (30) interposed therebetween.

Abstract: A method of manufacturing a semiconductor device having a microminiture trench isolation in which an insulating film is embedded by an HDP-CVD method comprising: a step of pre-planarization by conducting a dry etching selectively with respect to the insulating film laminated excessively on the surface of substrate, which is to be an active region, and a step of polishing by a CMP method in order to improve a surface planarity of the insulating film, wherein an etching mask used at the time of opening a trench opening portion has a multi-layer structure including a silicon nitride film and a polycrystal silicon film; the polycrystal silicon film is used as an etching stopper at the time of pre-planarization; and the silicon nitride film is used as an etching stopper at the time of polishing by a CMP method in order to remove simultaneously the excessive insulating film and the polycrystal silicon film to expose and a surface of the substrate, which is the active region, whereby the trench isolation having a sa

Abstract: There is described a method of manufacturing a semiconductor device, wherein a DRAM memory cell and a logic circuit are fabricated on a single semiconductor substrate, which method enables improvements in the refresh characteristics of the DRAM memory cell by preventing a leakage current from developing and enables improvements in the reliability of the semiconductor device, reduces power consumption, and enables improvements in the performance and processing speed of integrated circuits by assembly of the integrated circuits into a single chip. After formation of a polysilicon layer which is to act as gate electrodes, silicon nitride films are formed so as to cover source/drain regions of the DRAM memory cell and to cause other source/drain regions and the polysilicon layer to be exposed. A metal silicide layer is formed on the semiconductor substrate by means of self-aligned silicide technique.

Abstract: Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.

Abstract: A semiconductor device comprising a semiconductor substrate, a trench formed in the substrate and having an inner wall including a sidewall and a bottom surface, a silicon oxide film deposited on the inner wall, and a buried oxide film deposited on the silicon oxide film to bury the trench, wherein the sidewall has portions of a sidewall sloped at a first profile angle A1, a second profile angle A2 and a third profile angle A3 from a surface of the substrate toward the bottom surface of the trench, and the profile angles have a relationship of A1<A2, A3<A2 and A1<83°.

Abstract: A trench (21) is formed in a silicon substrate (1) on which an underlying oxide film (2) and a silicon nitride film (3) are formed. Then, a silicon oxide (11) is deposited by an HDP-CVD method to fill the trench (21) with the oxide. Further, a resist (41) including a second resist portion (42), and a resist (43) are formed. The silicon oxide film (11) that is not covered with the resists (41) and (43), is removed by dry etching. Etch selectivity of the silicon oxide film (11) to the stopper film (3) is not less than a value (2(c−a)/d) obtained by dividing twice a value (c−a) which is obtained by subtracting an alignment margin (a) from the maximum film thickness (c) of the silicon oxide film (11), by the film thickness (d) of the stopper film (3). The resists (41) and (43) are then removed, and the residual silicon oxide film (11B, 11DC, 11DE, 11FE) is polished and removed by the CMP method. This forms a trench type element isolation with no depression at its edge portion.

Abstract: There is provided a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having higher etching resistance than a CVD film are formed not only on the surroundings of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral sides of the imbedded oxide film projecting upward from the silicon substrate surface.

Abstract: A highly reliable semiconductor device and a manufacturing method thereof are provided, without lowering the mobility of carriers, by increasing the nitrogen concentration of part of a gate insulating film. Nitrogen containing regions containing nitrogen are provided on both end portions of a gate insulating film which is formed into a uniform thickness.

Abstract: The present invention provides a semiconductor device which includes trench-type element isolation which performs accurate alignment without deteriorating a device capability, and a method of manufacturing such a semiconductor device. Since a dummy gate electrode (14A) is formed in an edge proximity region of a trench (10A), a structure which does not create an etching remainder is realized. In addition, since a height difference is provided in a surface of the dummy gate electrode (14A) in such a manner that the height difference reflects a preliminary height difference between a surface of a silicon oxide films (2A) and a surface of a silicon substrate (1), it is possible to use the dummy gate electrode itself (14A) as an alignment mark.

Abstract: A gate electrode is made up of a polycrystalline silicon film containing phosphorous as a dopant for determining its conductivity type, a titanium silicide film of the C54 structure, and a tungsten silicide film all of which films are laid one on another in said order. A method of manufacturing a semiconductor device of the present invention involves sequentially forming a non-single-crystal silicon film containing a dopant for determining a conductivity type of the non-single-crystal silicon film, a titanium film, and a metal silicide film on a substrate. A titanium silicide film of a C49 and/or C54 structure is formed by performing a heat treatment so as to cause the titanium film to react with the non-single-crystal silicon film while reducing a first native oxide film formed in a first interface between the titanium film and the non-single-silicon film and a second native oxide film formed in a second interface between the titanium film and the metal silicide film.

Abstract: To obtain a semiconductor device which prevents an increase in the resistance of a source/drain region; which operates fast and stably; and which provides a high manufacturing yield, and to obtain a method of manufacturing the semiconductor device. A recess 8 is formed on a first low impurity-concentration region 5 with the exception of the area immediately below side wall insulating material 6y, and a layer damaged as a result of formation of the side wall insulating material 6y is removed. Further, a second low impurity-concentration region 10 is formed below the recess 8.

Abstract: An underlaid silicon oxide film (2) and a polycrystalline silicon film (5) are formed in this order on a surface (1S) of a silicon substrate (1). The polycrystalline silicon film (5) and the underlaid silicon oxide (2) are opened by anisotropic etching, to form a trench (21) extending to the inside of the semiconductor substrate (1). A silicon oxide film (11) formed by HDP-CVD is buried in the trench (21). A resist (41) is formed only on a surface of the silicon oxide film (11) in a device isolation region (20). The silicon oxide film (11) in an active region (30) is removed by dry etching with the resist (41) as a mask. After removing the resist (41), only the polycrystalline silicon film (5) is removed by dry etching. The underlaid oxide film (2) is removed by wet etching with hydrofluoric acid. By this method of manufacturing a semiconductor device, the surface of the semiconductor substrate and a trench-type device isolation are flattened effectively at low cost.

Abstract: In a semiconductor device with a trench-type element isolation structure, alignment can be performed with high accuracy without any deterioration in device performance. The surfaces of silicon oxide films (2B, 2C) embedded in trenches (10B, 10C) of an element forming region including a memory cell region (11B) and a peripheral circuit region (11C) in a semiconductor substrate (1), respectively, are almost level with the surface of the semiconductor substrate (1). On the other hand, the surface of a silicon oxide film (2A) embedded in a trench (10A) is formed lower than the surface of the semiconductor substrate (1).

Abstract: A semiconductor device comprising a semiconductor substrate, a trench formed in the substrate and having an inner wall including a sidewall and a bottom surface, a silicon oxide film deposited on the inner wall, and a buried oxide film deposited on the silicon oxide film to bury the trench, wherein the sidewall has portions of a sidewall sloped at a first profile angle A1, a second profile angle A2 and a third profile angle A3 from a surface of the substrate toward the bottom surface of the trench, and the profile angles have a relationship of A1<A2, A3<A2 and A1<83.degree..

Abstract: An insulator (5) is a frame element for covering the outer edges of the active region (3), and protrudes upwardly above the surface of a semiconductor substrate (1) to constitute part of the inner walls of a trench (9) filled with an insulating film (2). A gate oxide film (21) is formed on the surface of the active region (3) adjacent the center thereof. The etching rate of the insulator (5) is lower than that of the insulating film (2). The insulator (5) prevents the sidewalls of the insulating film (2) from being etched away to suppress the formation of the depression positioned lower than the surface of the semiconductor substrate (1), thereby to alleviate influences upon an electric field adjacent the outer edges of the active region (3).

Abstract: An element isolation region is formed in a silicon substrate by initially depositing an insulating film and first nitride film thereon, forming an opening therethrough exposing the substrate, and etching the substrate to form a groove. A polysilicon film and second nitride film are successively deposited, and the second nitride film is anisotropically etched to expose the polysilicon film at the bottom of the groove. The silicon substrate is then thermally oxidized using the first and second nitride films as a mask to form the element isolation region. In other embodiments, an oxide film is formed at the bottom of the groove prior or subsequent to deposition of the polysilicon film.