Patents by Inventor Takashi Kuroi
Takashi Kuroi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6661066Abstract: A semiconductor device and manufacturing method including a MOSFET having a trench-type element isolation structure (2) formed on a main surface of a semiconductor substrate (1). A pair of extensions (3) and source/drain regions (4) are selectively formed in the main surface so as to face each other through a channel region (50), a silicon oxide film (5) is formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) are formed on sides of the silicon oxide film (5), a gate insulating film (7) is formed on the main surface in a part where the channel region (50) is formed and a gate electrode (8) is formed to fill a recessed portion in an inversely tapered shape formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).Type: GrantFiled: September 22, 1999Date of Patent: December 9, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Kuroi, Yasuyoshi Itoh, Katsuyuki Horita, Katsuomi Shiozawa
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Publication number: 20030157755Abstract: A technique for preventing a decrease in alignment accuracy during a photolithography process is provided. A substrate (1) is prepared, in the surface (80) of which trenches (7) for use as alignment marks and trenches (17, 27) each forming an element isolation structure are formed and on the surface (80) of which a polysilicon film (3) is formed, avoiding the trenches (7, 17, 27). The trenches (7, 17, 27) are filled with an insulation film (30). The insulation film (30) is then selectively etched to partially remove the insulation film (30) in the trenches (7) and to leave the insulation film (30) on side and bottom surfaces (81, 82) of the trenches (7). Using the insulation film (30) in the trenches (7) as a protective film, the polysilicon film (3) is selectively etched. The use of the insulation film (30) in the trenches (7) as a protective film prevents the substrate (1) from being etched and thereby prevents the shape of the trenches (7) from being changed.Type: ApplicationFiled: August 6, 2002Publication date: August 21, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Masashi Kitazawa, Tomohiro Yamashita, Takashi Kuroi
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Publication number: 20030143810Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.Type: ApplicationFiled: January 28, 2003Publication date: July 31, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takashi Kuroi, Syuichi Ueno, Katsuyuki Horita
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Publication number: 20030127685Abstract: A semiconductor device less susceptible to inverse narrow channel effect and its manufacturing method are provided. A silicon nitride film (13) is adopted as element isolation regions; the silicon nitride film (13) has a smaller etch rate than a sacrificial silicon oxide film (7) which serves as a sacrificial layer during ion implantation (8). This prevents formation of recesses in the silicon nitride film (13) during the removal of the sacrificial silicon oxide film (7), which weakens the strength of the electric fields at the gate edges. Weakening the strength of the electric fields at the gate edges suppresses the inverse narrow channel effect, so that the MOS transistor offers a characteristic closer to a characteristic in which the threshold voltage keeps a constant value independently of the channel width. Thus an MOS transistor having a good characteristic can be manufactured.Type: ApplicationFiled: August 15, 2002Publication date: July 10, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Katsuomi Shiozawa, Takashi Kuroi, Katsuyuki Horita
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Patent number: 6577021Abstract: An SRAM of the present invention comprises a plurality of memory cells, which are formed over a plurality of wells, which store data and which do not have a well contact region for fixing the potential of the wells, and a plurality of well contact cells for fixing the potential of the wells that are formed over the plurality of wells so as to adjoin the memory cells, wherein the areas of the memory cells and the areas of the well contact cells are equal.Type: GrantFiled: March 14, 2002Date of Patent: June 10, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Chikayoshi Morishima, Yoshinori Okumura, Takashi Kuroi
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Publication number: 20030075744Abstract: Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16) function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.Type: ApplicationFiled: April 5, 2000Publication date: April 24, 2003Inventors: Katsuyuki Horita, Takashi Kuroi, Yasuyoshi Itoh, Katsuomi Shiozawa
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Patent number: 6548871Abstract: Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16)function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.Type: GrantFiled: April 5, 2000Date of Patent: April 15, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuyuki Horita, Takashi Kuroi, Yasuyoshi Itoh, Katsuomi Shiozawa
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Patent number: 6541825Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.Type: GrantFiled: March 15, 2001Date of Patent: April 1, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Kuroi, Syuichi Ueno, Katsuyuki Horita
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Publication number: 20030054597Abstract: A substrate surface (10S) is thermally oxidized to form an oxide film. The oxide film is patterned so that the substrate surface (10S) in an active region is exposed. An oxide film (20) is thereby provided. An exposed substrate surface (10S) is thermally oxidized, to form a thermal oxide film. This thermal oxide film is thereafter removed at least in an element forming region. A silicon film (41) is epitaxially grown on the exposed substrate surface (10S). Thereafter the silicon film (41) is polished by CMP to an extent that an upper surface of the silicon film after polishing is not more than an upper surface of the oxide film (20) in height. Next, the surface of the silicon film is thermally oxidized to form a thermal oxide film. After ion implantation of various types, this thermal oxide film is removed.Type: ApplicationFiled: August 6, 2002Publication date: March 20, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takashi Kuroi, Katsuyuki Horita, Katsuomi Shiozawa
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Patent number: 6521527Abstract: Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.Type: GrantFiled: August 7, 2001Date of Patent: February 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Kuroi, Shuichi Ueno, Hidekazu Oda, Satoshi Shimizu
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Patent number: 6503799Abstract: There is provided a method of forming an element isolation structure that can maintain its element isolation capability even with the progress of miniaturization of semiconductor elements. Through thermal processing in a nitrogen atmosphere at 900° C., a non single-crystal silicon film (80) is crystallized into single-crystal form by epitaxial growth on the main surface of a substrate, thereby to form an epitaxial silicon film (85). The epitaxial silicon film (85) is then planarized by CMP to expose the upper surface of an element isolation insulating film (50). This completes the element isolation insulating film (50) having a two-level protruding shape.Type: GrantFiled: November 26, 2001Date of Patent: January 7, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuyuki Horita, Takashi Kuroi, Shuuichi Ueno
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Patent number: 6498077Abstract: Provided are a semiconductor device having a MOS transistor of a structure capable of obtaining a good characteristic particularly about assurance of resistance to punch-through and leak current reduction, as well as a method of manufacturing the same. That is, in addition to the usual MOS transistor structure, a channel dope region (1) is disposed at a predetermined depth so as to extend substantially the entire surface of a flat surface in a P well region (22) including a channel region. In the channel dope region (1), it is set so that the maximum value of the P type impurity concentration (MAX of P) ranges from 1×1018 to 1×1019, and the maximum value of the N type impurity concentration (MAX of N) of a source/drain region (31 (32)) is not less than 10% and not more than 100%. Note that the surface proximate region of the P well region (22) is to be beyond the object.Type: GrantFiled: March 26, 2001Date of Patent: December 24, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shuuichi Ueno, Katsuyuki Horita, Takashi Kuroi
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Publication number: 20020190398Abstract: An SRAM of the present invention comprises a plurality of memory cells, which are formed over a plurality of wells, which store data and which do not have a well contact region for fixing the potential of the wells, and a plurality of well contact cells for fixing the potential of the wells that are formed over the plurality of wells so as to adjoin the memory cells, wherein the areas of the memory cells and the areas of the well contact cells are equal.Type: ApplicationFiled: March 14, 2002Publication date: December 19, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Chikayoshi Morishima, Yoshinori Okumura, Takashi Kuroi
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Patent number: 6482718Abstract: A method of manufacturing a semiconductor device is provided which, even if device dimensions decrease, prevents degradation in the operating characteristics of semiconductor elements which are isolated from each other by an element isolation region in a trench isolation structure. Implantation of ions (15) in a polycrystalline silicon layer (3) from above through a silicon nitride film (2) produces an ion-implanted polycrystalline silicon layer (16). Since the ions (15) are an ionic species of element which acts to enhance oxidation, the implantation of the ions (15) changes the polycrystalline silicon layer (3) into the ion-implanted polycrystalline silicon layer (16) having a higher oxidation rate. In subsequent formation of a thermal oxide film (21) on the inner wall of a trench (5), exposed part of the ion-implanted polycrystalline silicon layer (16) is also oxidized, forming relatively wide polycrystalline silicon oxide areas (21a).Type: GrantFiled: September 27, 2001Date of Patent: November 19, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Takashi Kuroi, Katsuyuki Horita
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Publication number: 20020158303Abstract: A MOSFET includes a silicon substrate (1) with trenches (2) formed therein. Each of the trenches (2) is completely filled with a silicon oxy-nitride (9) formed on inner wall faces (2W) and a bottom face (2B) thereof. The ratio between compositions of the silicon oxy-nitride (9) is controlled so that the silicon oxy-nitride (9) is approximately equal in thermal expansion coefficient to silicon. An end portion of the silicon oxy-nitride (9) along an opening of each trench (2) is located at a higher level than a main surface (1S) of the silicon substrate (1), and a surface of the silicon oxy-nitride (9) increases in height from the end portion toward the center thereof. The silicon oxy-nitride (9) has no depressions adjacent to the end portion thereof. Sidewall oxide films (41) and a gate electrode (5) are formed on a gate insulation film (4) formed in an active region.Type: ApplicationFiled: June 19, 2002Publication date: October 31, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takashi Kuroi, Hidekazu Oda, Yukio Nishida
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Publication number: 20020151143Abstract: A method of manufacturing a semiconductor device is provided which, even if device dimensions decrease, prevents degradation in the operating characteristics of semiconductor elements which are isolated from each other by an element isolation region in a trench isolation structure. Implantation of ions (15) in a polycrystalline silicon layer (3) from above through a silicon nitride film (2) produces an ion-implanted polycrystalline silicon layer (16). Since the ions (15) are an ionic species of element which acts to enhance oxidation, the implantation of the ions (15) changes the polycrystalline silicon layer (3) into the ion-implanted polycrystalline silicon layer (16) having a higher oxidation rate. In subsequent formation of a thermal oxide film (21) on the inner wall of a trench (5), exposed part of the ion-implanted polycrystalline silicon layer (16) is also oxidized, forming relatively wide polycrystalline silicon oxide areas (21a).Type: ApplicationFiled: September 27, 2001Publication date: October 17, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Katsuomi Shiozawa, Takashi Kuroi, Katsuyuki Horita
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Publication number: 20020127841Abstract: There is provided a method of forming an element isolation structure that can maintain its element isolation capability even with the progress of miniaturization of semiconductor elements. Through thermal processing in a nitrogen atmosphere at 900° C., a non single-crystal silicon film (80) is crystallized into single-crystal form by epitaxial growth on the main surface of a substrate, thereby to form an epitaxial silicon film (85). The epitaxial silicon film (85) is then planarized by CMP to expose the upper surface of an element isolation insulating film (50). This completes the element isolation insulating film (50) having a two-level protruding shape.Type: ApplicationFiled: November 26, 2001Publication date: September 12, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Katsuyuki Horita, Takashi Kuroi, Shuuichi Uneo
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Patent number: 6399985Abstract: Provided are a semiconductor device that can obtain more output current without increasing the occupied area of a MOS transistor, and a method for manufacturing the same. MOS transistors (M11, M12) are electrically isolated by a trench isolation oxide film (21). The MOS transistor (M11) has a groove portion (GP) in which the width of the top is 20 nm to 80 nm and the depth is 50 nm to 150 nm. The groove portion (GP) is disposed at the boundary part between a trench isolation insulating film (22) and an active region (AR1) so as to surround the active region (AR1). A gate electrode (31A) is not only disposed above the active region (AR1) but also buried in the groove (GP) with a gate oxide film (30) interposed therebetween.Type: GrantFiled: January 2, 2001Date of Patent: June 4, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuyuki Horita, Takashi Kuroi, Yoshinori Okumura
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Patent number: 6383884Abstract: A semiconductor device includes a silicon substrate (1), a pair of isolating insulation films (9), a channel region (2), a pair of source/drain regions (3), a pair of silicon oxide films (4) formed on an upper surface of the silicon substrate (1) so as to overlie the source/drain regions (3), and a gate structure (8) formed in a first recess defined by the upper surface of the silicon substrate (1) over the channel region (2) and side surfaces of the pair of silicon oxide films (4). The gate structure (8) includes a gate oxide film (5) formed on the upper surface of the silicon substrate (1), a pair of silicon oxide films (6) formed on lower part of the side surfaces of the pair of silicon oxide films (4), and a metal film (7) filling a second recess surrounded by upper part of the side surfaces of the silicon oxide films (4), the silicon oxide films (6) and the gate oxide film (5).Type: GrantFiled: February 2, 2000Date of Patent: May 7, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Katsuomi Shiozawa, Takashi Kuroi, Yasuyoshi Itoh, Katsuyuki Horita
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Patent number: 6372604Abstract: There is provided a method for forming a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having higher etching resistance than the CVD film are formed not only on the surroundings of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral sides of the imbedded oxide film projecting upward from the silicon substrate surface.Type: GrantFiled: May 21, 2001Date of Patent: April 16, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Maiko Sakai, Takashi Kuroi, Katsuyuki Horita