Abstract: A semiconductor memory device is provided with plural memory cells, plural bit lines BL, each bit line being commonly connected to the plural memory cells that are arranged in the same row, plural word lines WL and plural plate lines CP, each word line and each plate line being commonly connected to the plural memory cells that are arranged in the same column, plural plate voltage supply lines CPS arranged in the column direction, and means for electrically connecting each of the plural plate voltage supply lines to each of the corresponding plural plate lines.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

Abstract: A memory cell array is composed of a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a capacitor having a plate electrode connected to a common cell plate and a storage electrode; and a transistor provided between the storage electrode of the capacitor and a bit line, with a gate connected to a word line. A first amplifier amplifies an I/O line pair to a first voltage and a second voltage higher than the first voltage. A second amplifier amplifies a bit line pair to the first voltage and a third voltage higher than the second voltage. A switch element switches the connection relationship between the I/O line pair and the bit line pair among a connected state, a disconnected state and a transmission limited state in which the potential transmitted is limited.

Abstract: It is an object of the present invention to provide a conductive member for use in OA equipment which shows very stable conductivity in the volume resistivity range of 105 to 1012 ?·cm, the conductivity of which is less dependent on the voltage applied and varies only slightly during continuous energization and upon changes in environmental factors such as temperature and humidity and which will not stain photoconductors due to bleeding or blooming. The present invention provides a conductive member for OA equipment, which is obtainable by molding a composition comprising a non-ether-based polyurethane and bis(trifluoromethanesulfonyl)imidolithium.

Abstract: A semiconductor memory device comprises plural memory cells MC arranged in a matrix, plural bit lines BL and plural plate line voltage supply lines SCP which are arranged in a row direction, plural sense amplifier circuits SA which are arranged in a column direction and are electrically connected to the respective bit lines, plural plate line voltage supply circuits CPD which are arranged in the column direction and drive the plate line voltage supply lines SCP, and means for electrically connecting the plate line voltage supply lines SCP with the plural plate lines CP, wherein the respective plate voltage supply lines SCP are electrically connected, at different positions on the same plate line CP, to the plate line CP.

Abstract: Disclosed are a mouse homozygous or heterozygous for the defect of the Noc2 gene, and a tissue and a cell of the mouse. The Noc2 knockout mice, which exhibit stress-related insulin hyposecretion and accumulation of secretory granules of increased size and irregular shape in exocrine cells, provide a test system used in the development of therapeutic drugs for related disorders.

Abstract: An object of the present invention is to provide, in an FeRAM memory device fixed to a cell plate, a memory device in which RES_N (source line) of a reset transistor for resetting a storage node has a low resistance. A memory cell (101) includes a ferroelectric capacitance, a first MOS transistor for selecting the memory cell, and a second MOS transistor which is a reset transistor for resetting the storage node. Potential is supplied to RES_N (source line) (impurity activation region) of the second MOS transistor through the following two conductive layers: an impurity activation region which is a conductive layer below an upper electrode of the ferroelectric capacitance, and a bit-line formation wiring layer making up a bit line BL. This configuration makes it possible to supply potential to RES_N (source line) with a low resistance and perform a stable operation.

Abstract: To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

Abstract: Mice homozygous for the lack of inward-rectifying potassium channel Kir6.1 gene are disclosed. The mice causes a high incidence of sudden death associated with arrhythmia (atrioventricular block) caused by spontaneous cardiac ischemia, a condition similar to Prinzmetal angina (variant angina) in human, representing an animal model of Prinzmetal angina. Mice heterozygous for the lack of inward-rectifying potassium channel Kir6.1 gene are also disclosed, which are used as parent mice for reproduction of the homozygous mice.

Abstract: The present invention provides a TGR5 receptor agonist comprising a fused ring compound represented by the formula wherein ring A is an optionally substituted aromatic ring; and ring B? is a 5- to 8-membered ring having one or more substituents or a salt thereof or a prodrug thereof, which is useful for the treatment of various diseases.

Abstract: A tape printing apparatus including an internal unit having a print mechanism, a cutting mechanism, and a tape discharge mechanism that safely and reliably discharges tapes at a suitable speed to a proximate location relative to an apparatus main body. When printing a tape accommodated in a tape cassette by a thermal head, cutting the tape using a fixed blade and a movable blade and forcibly discharging the tape by a driving roller and a pressing roller, a bisectrix that bisects the width of the tape in a vertical direction is located further upward by a length L2 than a bisectrix of the driving roller and the pressing roller. As a result, the cut end of the tape will be rotated and gradually directed upward in the course of delivery of the tape by the driving roller and the pressing roller to discharge the tape outside of the apparatus main body through the tape discharge slot in a obliquely maintained position.

Abstract: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

Abstract: A semiconductor memory device having a memory cell array in which plural memory transistors and plural memory call capacitors, which are components of memory cells, are arranged, comprises a first wiring layer formed on the memory cell array, and a second wiring layer formed above the first wiring layer, wherein a wiring density of the first wiring layer on the memory cell array is higher than a wiring density of the second wiring layer on the memory cell array. Therefore, a hydrogen barrier property for the capacitors is improved, and an adverse effect due to stress applied to the capacitors is reduced, thereby suppressing deterioration of capacitor characteristics.

Abstract: A cryogenic system includes a containment vessel in which a body to be cooled is housed in such a manner that the body is immersed in a liquid coolant; a tubular refrigerator sleeve; and a refrigerator, inserted in the opening section of the refrigerator sleeve, for recondensing coolant gas generated from the coolant, wherein a gas flow-forming means for forming a flow of purge gas toward an opening section of the refrigerator sleeve is provided. The purge gas prevents air from entering a refrigerator sleeve during the replacement of a refrigerator of a cryogenic system.

Abstract: Disclosed are a mouse homozygous or heterozygous for the defect of the Noc2 gene, and a tissue and a cell of the mouse. The Noc2 knockout mice, which exhibit stress-related insulin hyposecretion and accumulation of secretory granules of increased size and irregular shape in exocrine cells, provide a test system used in the development of therapeutic drugs for related disorders.

Abstract: To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost. A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

Abstract: A ferroelectric memory of the present invention comprises: a plurality of normal cells, each of which includes a first ferroelectric capacitor for holding data and a first transistor connected to a first electrode of the first ferroelectric capacitor; a first bit line connected to the first transistor; a first bit line precharge circuit which is a switch circuit provided between the first bit line and a ground; and a word line connected to a gate of the first transistor. The word line is deactivated to disconnect the first ferroelectric capacitor from the first bit line before the first bit line precharge circuit is driven to discharge a potential of the first bit line.

Abstract: A conductive member for OA equipment (electrophotographic apparatus or electrostatic recording apparatus) which is obtainable from a composition comprising a non-ether-based polyurethane, carbon black and bis(trifluoromethanesulfonyl)imidolithium. The conductive member shows very stable conductivity in the volume resistivity range of 105 to 1012 ?·cm, the conductivity of which is less dependent on the voltage applied and varies only slightly during continuous energization and upon changes in environmental factors such as temperature and humidity.

Abstract: There is disclosed an advantageous mixed acid anhydride production method of formula (1): R1C(O)OY(O)n(R2)p??(1) wherein R1, R2 and Y denote the same as defined below, n and p denote an integer of 1 or 2, which is characterized by adding a carboxylic acid of formula (2); R1COOH??(2) wherein R1 denotes a hydrogen atom, an optionally substituted alkyl group or the like, an organic base to a solution of a carboxylic acid activating agent of formula (3); (R2)pY(O)nX??(3) wherein R2 denotes an optionally substituted aliphatic hydrocarbyl group or the like, Y denotes a carbon atom, a phosphorus atom, or a sulfur atom, and X denotes a chlorine atom or the like.

Abstract: A tape printing apparatus including an internal unit having a print mechanism, a cutting mechanism, and a tape discharge mechanism that safely and reliably discharges tapes at a suitable speed to a proximate location relative to an apparatus main body. When printing a tape accommodated in a tape cassette by a thermal head, cutting the tape using a fixed blade and a movable blade and forcibly discharging the tape by a driving roller and a pressing roller, a bisectrix that bisects the width of the tape in a vertical direction is located further upward by a length L2 than a bisectrix of the driving roller and the pressing roller. As a result, the cut end of the tape will be rotated and gradually directed upward in the course of delivery of the tape by the driving roller and the pressing roller to discharge the tape outside of the apparatus main body through the tape discharge slot in a obliquely maintained position.