Patents by Inventor Takashi Nakabayashi
Takashi Nakabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070138571Abstract: A threshold control layer of a second MIS transistor is formed under the same conditions for forming a threshold control layer of a first MIS transistor. LLD regions of the second MIS transistor are formed under the same conditions for forming LDD regions of a third transistor.Type: ApplicationFiled: October 10, 2006Publication date: June 21, 2007Inventors: Takashi Nakabayashi, Hideyuki Arai, Mitsuo Nissa
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Publication number: 20070131997Abstract: A semiconductor device includes a capacitor formed by successively stacking a lower electrode, a capacitor dielectric film and an upper electrode on a substrate. The lower electrode includes a first conducting layer and a second conducting layer formed on the first conducting layer and having higher resistivity than the first conducting layer, and the capacitor dielectric film is formed so as to be in contact with the second conducting layer of the lower electrode.Type: ApplicationFiled: September 19, 2006Publication date: June 14, 2007Inventors: Takashi Ohtsuka, Takashi Nakabayashi, Yoshiyuki Shibata
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Publication number: 20070066012Abstract: A semiconductor device comprises a capacitor formed by sequentially stacking a lower electrode, a capacitor insulating film, and an upper electrode over a substrate. The capacitor insulating film is made of Hf oxide or Zr oxide, and between the lower electrode and the capacitor insulating film, a first barrier film is formed which is made of Hf oxide or Zr oxide containing at least either of Al and Si.Type: ApplicationFiled: May 22, 2006Publication date: March 22, 2007Inventors: Takashi Ohtsuka, Takashi Nakabayashi
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Publication number: 20060292799Abstract: A memory embedded semiconductor device according to the present invention has a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate. The logic transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed in the semiconductor substrate each having a silicide film formed thereon. On the other hand, the memory transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed in the semiconductor substrate each having a silicide film formed thereon to be thinner than the silicide film formed on each of the source/drain diffusion layers of the logic transistor.Type: ApplicationFiled: August 29, 2006Publication date: December 28, 2006Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Takashi Nakabayashi
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Patent number: 7126174Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: November 24, 2004Date of Patent: October 24, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Patent number: 7109536Abstract: A memory embedded semiconductor device according to the present invention has a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate. The logic transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed in the semiconductor substrate each having a silicide film formed thereon. On the other hand, the memory transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed in the semiconductor substrate each having a silicide film formed thereon to be thinner than the silicide film formed on each of the source/drain diffusion layers of the logic transistor.Type: GrantFiled: November 3, 2004Date of Patent: September 19, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Nakabayashi
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Publication number: 20060086960Abstract: A capacitor of a semiconductor memory of the present invention includes: a lower electrode which covers the surface of a storage node hole from the bottom to at least one of the sidewalls up to a level lower than the top surface of a second interlayer insulating film; a capacitive insulating film which covers the lower electrode; and an upper electrode which covers the capacitive insulating film.Type: ApplicationFiled: June 15, 2005Publication date: April 27, 2006Inventors: Hideyuki Arai, Takashi Nakabayashi, Takashi Ohtsuka
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Publication number: 20060076600Abstract: In a method for fabricating a semiconductor device according to the present invention, a groove is formed in a second interlayer insulating film, and then a storage electrode is formed which covers bottom and side surfaces of the groove. A capacitor insulating film is formed on the storage electrode, and a CVD method at a low temperature of 400° C. or lower and annealing with ammonia are repeated to form a TiOxNy film on the capacitor insulating film. A TiN film is formed on the TiOxNy film, and the TiN film is etched using the TiOxNy film as a stopper. The exposed TiOxNy film is then removed to form a plate electrode made of the TiOxNy film and the TiN film.Type: ApplicationFiled: July 26, 2005Publication date: April 13, 2006Inventors: Takashi Nakabayashi, Hideyuki Arai, Takashi Ohtsuka, Hisashi Yano
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Patent number: 6967409Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: June 5, 2003Date of Patent: November 22, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Publication number: 20050156220Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: ApplicationFiled: March 17, 2005Publication date: July 21, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Patent number: 6906382Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween, and a sidewall spacer is then formed at the lateral sides of the gate electrode on the semiconductor substrate. Epitaxial growth is conducted at a lower growth rate to form, at both lateral sides of the sidewall spacer on the semiconductor substrate, first semiconductor layers made of first single-crystal silicon films superior in crystallinity. Then, epitaxial growth is conducted at a higher growth rate to form, on the first semiconductor layers, second semiconductor layers made of single-crystal films or polycrystalline films, which are inferior in crystallinity, or amorphous films. The upper areas of the first semiconductor layers and the whole areas of the second semiconductor layers are doped with impurity, thus forming impurity diffusion layers respectively serving as a source and a drain.Type: GrantFiled: October 3, 2001Date of Patent: June 14, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Nakabayashi
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Publication number: 20050101076Abstract: A memory embedded semiconductor device according to the present invention has a memory region having a memory transistor and a logic region having a logic transistor each provided in a common semiconductor substrate. The logic transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed in the semiconductor substrate each having a silicide film formed thereon. On the other hand, the memory transistor has a gate electrode provided on the semiconductor substrate and source/drain diffusion layers formed in the semiconductor substrate each having a silicide film formed thereon to be thinner than the silicide film formed on each of the source/drain diffusion layers of the logic transistor.Type: ApplicationFiled: November 3, 2004Publication date: May 12, 2005Inventor: Takashi Nakabayashi
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Publication number: 20050093089Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: ApplicationFiled: November 24, 2004Publication date: May 5, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Patent number: 6876682Abstract: A light generating module 1 comprises a housing 2, a semiconductor light-emitting device 4, a driving element 6, and a monitoring light-receiving device 8. The monitoring light-receiving device 8 is optically coupled with the semiconductor light-emitting device 4. The driving element 6 drives the semiconductor light-emitting device 4. The housing 2 contains the semiconductor light-emitting device 4, the driving element 6, and the monitoring light-receiving device 8. These elements 4, 6, and 8 are disposed sequentially along a predetermined axis. The driving element 6 is disposed between the semiconductor light-emitting device 4 and the monitoring light-receiving device 8. This configuration makes it possible to dispose the driving element 6 close to the semiconductor light-emitting device 4 so as to achieve a transmission rate of 10 Gbps without degrading the optical coupling between the semiconductor light-receiving device 8 and the semiconductor light-emitting device 4.Type: GrantFiled: February 22, 2002Date of Patent: April 5, 2005Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Nakabayashi, Atsushi Hamakawa
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Patent number: 6847119Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: June 5, 2003Date of Patent: January 25, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Patent number: 6758607Abstract: A package contains therein a semiconductor laser element for emitting light and a semiconductor circuit element for driving the semiconductor laser element and is provided with an optical fiber supporting face and a back face. The optical fiber supporting face is provided for supporting an optical fiber for transmitting the light from the semiconductor laser element, and the back face is opposed to the optical fiber supporting face. The back face has a lead pin for feeding a positive-phase signal into the semiconductor circuit element and a lead pin for feeding a negative-phase signal into the semiconductor circuit element. The lead pins penetrate through the back face. The semiconductor circuit element receives positive-phase and complementary negative-phase signals, both including a high-frequency component of 10 GHz or higher, through the lead pins, converts these signals into a single-ended signal, and outputs the resulting signal to the semiconductor laser element.Type: GrantFiled: March 11, 2002Date of Patent: July 6, 2004Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Nakabayashi, Noriaki Kaida
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Patent number: 6747320Abstract: A semiconductor device is provided in which the difference in characteristics between a pair of sense amplifier transistors of a DRAM is suppressed, whereby the sensitivity of a sense amplifier is enhanced. A pair of gate electrodes of a N-type sense amplifier transistor and a pair of gate electrodes of a P-type sense amplifier transistor constituting a CMOS sense amplifier of the DRAM respectively are placed in parallel to each other in one active region in the same direction as that of bit lines. A pair of adjacent N-type sense amplifier transistors and a pair of adjacent P-type sense amplifier transistors are isolated by STI.Type: GrantFiled: July 18, 2003Date of Patent: June 8, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Nakabayashi
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Patent number: 6709950Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.Type: GrantFiled: July 11, 2001Date of Patent: March 23, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Mizuki Segawa, Isao Miyanaga, Toshiki Yabu, Takashi Nakabayashi, Takashi Uehara, Kyoji Yamashita, Takaaki Ukeda, Masatoshi Arai, Takayuki Yamada, Michikazu Matsumoto
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Publication number: 20040026759Abstract: A semiconductor device is provided in which the difference in characteristics between a pair of sense amplifier transistors of a DRAM is suppressed, whereby the sensitivity of a sense amplifier is enhanced. A pair of gate electrodes of a N-type sense amplifier transistor and a pair of gate electrodes of a P-type sense amplifier transistor constituting a CMOS sense amplifier of the DRAM respectively are placed in parallel to each other in one active region in the same direction as that of bit lines. A pair of adjacent N-type sense amplifier transistors and a pair of adjacent P-type sense amplifier transistors are isolated by STI.Type: ApplicationFiled: July 18, 2003Publication date: February 12, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Nakabayashi
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Patent number: 6674111Abstract: An etch stopper member is formed under a cell plate electrode so as to surround an active region along a periphery of the cell plate electrode. The etch stopper member is formed from a material that is resistant to an etchant of a first interlayer insulating film. For example, a dummy gate line and a cylindrical wall formed thereon are provided as the etch stopper member. Either the dummy gate line or the cylindrical wall may be provided as the etch stopper member. The etch stopper member prevents the interlayer insulating film from being laterally etched at the boundary between a DRAM memory section and a logic section. This eliminates the need to provide an etching margin, allowing for reduction in the area of the DRAM memory section.Type: GrantFiled: August 17, 2001Date of Patent: January 6, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Takashi Nakabayashi