Patents by Inventor Takashi Shinohe

Takashi Shinohe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220158000
    Abstract: Provided is a semiconductor device in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented, the semiconductor device that is particularly useful for power devices. A semiconductor device including at least: a semiconductor layer; a Schottky electrode; and an insulator layer provided between a part of the semiconductor layer and the Schottky electrode, wherein the semiconductor layer contains a crystalline oxide semiconductor, and wherein the insulator layer has a taper angle of 10° or less.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 19, 2022
    Inventors: Mitsuru OKIGAWA, Yasushi HIGUCHI, Yusuke MATSUBARA, Osamu IMAFUJI, Takashi SHINOHE
  • Publication number: 20220140145
    Abstract: Provided are a multilayer structure in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented and a semiconductor device using the multilayer structure, the multilayer structure and the semiconductor device that are particularly useful for power devices. A multilayer structure in which an insulator film is arranged on a part of a semiconductor film, wherein the semiconductor film has a corundum structure and contains a crystalline oxide semiconductor containing one or two or more metals selected from groups 9 and 13 of the periodic table, and wherein the insulator film has a taper angle of 20° or less.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Inventors: Mitsuru OKIGAWA, Yasushi HIGUCHI, Yusuke MATSUBARA, Osamu IMAFUJI, Takashi SHINOHE
  • Publication number: 20220130952
    Abstract: An object of the disclosure is to provide a semiconductor device having enhanced adhesion of the electrode while improving the reverse direction breakdown voltage, which is especially useful for power devices. A semiconductor device including a semiconductor layer and an electrode layer provided on the semiconductor layer and including at least a first electrode layer and a second electrode layer provided on the first electrode layer, wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer, wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from that of the semiconductor layer, and wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in plan view.
    Type: Application
    Filed: October 22, 2021
    Publication date: April 28, 2022
    Inventors: Mitsuru OKIGAWA, Hideaki YANAGIDA, Takashi SHINOHE
  • Patent number: 11233129
    Abstract: The disclosure provides a semiconductor apparatus capable of keeping a semiconductor characteristics and realizing excellent semiconductor properties even when using an n type semiconductor (gallium oxide, for example) having a low loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC. A semiconductor apparatus including at least an n type semiconductor layer and a p+ type semiconductor layer, wherein the n type semiconductor layer includes a crystalline oxide semiconductor (gallium oxide, for example) containing a metal of Group 13 of the periodic table as a main component, and the p+ type semiconductor layer includes a crystalline oxide semiconductor (iridium oxide, for example) containing a metal of Group 9 of the periodic table as a main component.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: January 25, 2022
    Assignee: FLOSFIA INC.
    Inventors: Tokiyoshi Matsuda, Isao Takahashi, Takashi Shinohe
  • Publication number: 20210328062
    Abstract: A semiconductor device including at least one inversion channel region includes an oxide semiconductor film containing a crystal that has a corundum structure at the inversion channel region.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 21, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE
  • Publication number: 20210328026
    Abstract: A layered structure includes an oxide semiconductor film containing as a major component gallium oxide or a mixed crystal thereof, and an oxide film containing at least one element selected from elements of Group 15 in the periodic table and arranged on the oxide semiconductor film.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 21, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE
  • Patent number: 11152472
    Abstract: A crystalline oxide semiconductor with excellent crystalline qualities that is useful for semiconductors requiring heat dissipation is provided. A crystalline oxide semiconductor including a first crystal axis, a second crystal axis, a first side, and a second side that is shorter than the first side, a linear thermal expansion coefficient of the first crystal axis is smaller than a linear thermal expansion coefficient of the second crystal axis, a direction of the first side is parallel and/or substantially parallel to a direction of the first crystal axis, and a direction of the second side is parallel and/or substantially parallel to a direction of the second crystal axis.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 19, 2021
    Assignees: FLOSFIA INC., DENSO CORPORATION
    Inventors: Isao Takahashi, Tatsuya Toriyama, Masahiro Sugimoto, Takashi Shinohe, Hideyuki Uehigashi, Junji Ohara, Fusao Hirose, Hideo Matsuki
  • Publication number: 20210320179
    Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; one or more p-type semiconductors; an electrode, the one or more p-type semiconductors that are provided between the n-type semiconductor layer and the electrode, and at least a part of the one or more p-type semiconductors is protruded in the electrode.
    Type: Application
    Filed: July 10, 2019
    Publication date: October 14, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE, Koji AMAZUTSUMI
  • Publication number: 20210320176
    Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; an electrode; two or more p-type semiconductors that is provided between the n-type semiconductor layer and the electrode, the n-type semiconductor layer containing gallium, a number of the two or more p-type semiconductors that is equal to or more than three, and the two or more p-type semiconductors that are embedded in the n-type semiconductor layer.
    Type: Application
    Filed: July 10, 2019
    Publication date: October 14, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE, Koji AMAZUTSUMI
  • Publication number: 20210296511
    Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; an electrode; two or more p-type semiconductors provided between the n-type semiconductor layer and the electrode, the n-type semiconductor layer containing a corundum-structured crystallin oxide semiconductor as a major component, a number of the two or more p-type semiconductor that is equal to or more than three, and the two or more p-type semiconductors that are embedded in the n-type semiconductor layer.
    Type: Application
    Filed: July 10, 2019
    Publication date: September 23, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE, Koji AMAZUTSUMI
  • Publication number: 20210272805
    Abstract: The disclosure provides a film forming method that enables to obtain an epitaxial film with reduced defects such as dislocations due to a reduced facet growth industrially advantageously, even if the epitaxial film has a corundum structure. When forming an epitaxial film on a crystal-growth surface of a corundum-structured crystal substrate directly or via another layer, using the crystal substrate having an uneven portion on the crystal-growth surface of the crystal substrate, generating and floating atomized droplets by atomizing a raw material solution including a metal; carrying the floated atomized droplets onto a surface of the crystal substrate by using a carrier gas; and causing a thermal reaction of the atomized droplets in a condition of a supply rate limiting state.
    Type: Application
    Filed: June 21, 2019
    Publication date: September 2, 2021
    Inventors: Isao TAKAHASHI, Takashi SHINOHE
  • Publication number: 20210226002
    Abstract: The disclosure provides a crystalline oxide film that has reduced defects such as dislocations due to a reduced facet growth. Also, the disclosure provides a crystalline oxide film that is useful for semiconductor devices and has an enhanced crystal quality. A crystalline oxide film, including: an epitaxial layer having a corundum structure, the lateral growth area is substantially free from a facet growth area, a growth direction of the lateral growth area that is c-axis direction or substantially c-axis direction, the lateral growth area including a dislocation line extending to the c-axis direction or substantially c-axis direction, a first crystal oxide and a second crystal oxide bonded to each other, that are crystal-grown in a direction parallel or approximately parallel to the x-axis.
    Type: Application
    Filed: June 21, 2019
    Publication date: July 22, 2021
    Inventors: Isao TAKAHASHI, Takashi SHINOHE
  • Patent number: 10944015
    Abstract: In a first aspect of a present inventive subject matter, a semiconductor device includes an n-type semiconductor layer including a first semiconductor as a major component, an i-type semiconductor layer including a second semiconductor as a major component and a p-type semiconductor layer including a third semiconductor as a major component. The second semiconductor contains a corundum-structured oxide semiconductor.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 9, 2021
    Assignee: FLOSFIA INC.
    Inventors: Masahiro Sugimoto, Isao Takahashi, Takashi Shinohe, Toshimi Hitora
  • Patent number: 10943981
    Abstract: In a first aspect of a present inventive subject matter, a semiconductor device includes an n-type semiconductor layer, an i-type semiconductor layer and a p-type semiconductor layer. The i-type semiconductor layer includes an oxide semiconductor as a major component. The oxide semiconductor that is included as the major component of the i-type semiconductor layer includes at least one metal selected from among aluminum, indium, and gallium.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 9, 2021
    Assignee: FLOSFIA INC.
    Inventors: Masahiro Sugimoto, Isao Takahashi, Takashi Shinohe, Toshimi Hitora
  • Patent number: 10927458
    Abstract: In a first aspect of a present inventive subject matter, a method of forming a film includes turning a raw material containing at least a first chemical element and a second chemical element into atomized droplets; carrying the atomized droplets containing at least the first chemical element and the second chemical element by use of a carrier gas onto an object; and causing a reaction of the atomized droplets to form a film containing at least the first chemical element and the second chemical element on the object. The first chemical element is selected from among elements of Group 14 and elements of Group 15 of the periodic table. The second chemical element is selected from among d-block elements, elements of Group 13 and elements of Group 14 of the periodic table and different from the first chemical element.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: February 23, 2021
    Assignee: FLOSFIA INC.
    Inventors: Shingo Yagyu, Takahiro Sasaki, Nobuaki Watanabe, Takashi Shinohe
  • Patent number: 10930743
    Abstract: In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer including an ?-phase crystalline oxide semiconductor with a first composition, and a second semiconductor layer including an ?-phase crystalline oxide semiconductor with a second composition that is different from the first composition of the first semiconductor layer, and the second semiconductor layer is layered on the first semiconductor layer.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: February 23, 2021
    Assignee: FLOSFIA INC.
    Inventors: Tokiyoshi Matsuda, Takashi Shinohe, Toshimi Hitora
  • Publication number: 20210013311
    Abstract: A semiconductor device including at least an inversion channel region includes an oxide semiconductor film containing a crystal that contains at least gallium oxide at the inversion channel region.
    Type: Application
    Filed: July 11, 2019
    Publication date: January 14, 2021
    Inventors: Masahiro SUGIMOTO, Isao TAKAHASHI, Takashi SHINOHE
  • Publication number: 20200403070
    Abstract: A semiconductor apparatus capable of reducing the leakage current in the reverse direction, and keeping characteristics thereof, even when using n type semiconductor (gallium oxide, for example) or the like having a low-loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC is provided. A semiconductor apparatus includes a crystalline oxide semiconductor having a corundum structure as a main component, and an electric field shield layer and a gate electrode that are respectively laminated directly or through other layers on the n type semiconductor layer, wherein the electric field shield layer includes a p type oxide semiconductor, and is embedded in the n type semiconductor layer deeper than the gate electrode.
    Type: Application
    Filed: November 15, 2018
    Publication date: December 24, 2020
    Applicant: FLOSFIA INC.
    Inventors: Tokiyoshi MATSUDA, Masahiro SUGIMOTO, Takashi SHINOHE
  • Publication number: 20200395450
    Abstract: The disclosure provides a semiconductor apparatus capable of keeping a semiconductor characteristics and realizing excellent semiconductor properties even when using an n type semiconductor (gallium oxide, for example) having a low loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC. A semiconductor apparatus includes a gate electrode and a channel layer formed of a channel directly or through other layers on a side wall of the gate electrode, and wherein a portion of or whole the channel layer may be a p type oxide semiconductor (iridium oxide, for example).
    Type: Application
    Filed: November 15, 2018
    Publication date: December 17, 2020
    Inventors: Tokiyoshi MATSUDA, Masahiro SUGIMOTO, Takashi SHINOHE
  • Publication number: 20200395449
    Abstract: The disclosure provides a semiconductor apparatus capable of keeping a semiconductor characteristics and realizing excellent semiconductor properties even when using an n type semiconductor (gallium oxide, for example) having a low loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC. A semiconductor apparatus including at least an n type semiconductor layer and a p+ type semiconductor layer, wherein the n type semiconductor layer includes a crystalline oxide semiconductor (gallium oxide, for example) containing a metal of Group 13 of the periodic table as a main component, and the p+ type semiconductor layer includes a crystalline oxide semiconductor (iridium oxide, for example) containing a metal of Group 9 of the periodic table as a main component.
    Type: Application
    Filed: November 15, 2018
    Publication date: December 17, 2020
    Inventors: Tokiyoshi MATSUDA, Isao TAKAHASHI, Takashi SHINOHE