Abstract: A gate driving circuit of embodiments is provided with a first transistor which controls a gate-on voltage applied to a gate electrode of a switching device, a second transistor which controls a gate-off voltage applied to the gate electrode of the switching device, a driving logic circuit which controls turn-on/turn-off of the first and second transistors, a first power source which supplies the gate-on voltage to the gate electrode when the first transistor is turned on, a second power source which supplies the gate-off voltage to the gate electrode when the second transistor is turned on, a first gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, a second gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, and a gate resistance control circuit which controls gate voltages of a plurality of field effect transistors.

Abstract: A semiconductor device according to an embodiment includes: a first electrode; a SiC semiconductor layer including n-type semiconductor; and a second electrode including a SiC metallic region made of metal in contact with the SiC semiconductor layer, the SiC metallic region provided on a side of the SiC semiconductor layer opposite to the first electrode, the SiC metallic region containing at least one element selected from the group of Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), Sc (scandium), Y (yttrium), La (lanthanum), and lanthanoid (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu).

Abstract: In a manufacturing method for a semiconductor device according to an embodiment, a first heat treatment to anneal or oxidize an SiC layer in an atmosphere where a gas including carbon (C) exists is applied. Further, the semiconductor device according to the embodiment includes: an SiC substrate having a first surface and a second surface; a first conductivity type SiC layer disposed on the first surface side of the SiC substrate, and including a low level density region having Z1/2 level density of 1×1011 cm?3 or less measured by deep level transient spectroscopy (DLTS); a second conductivity type SiC region disposed on a surface of the SiC layer; a first electrode disposed on the SiC region; and a second electrode disposed on the second surface side of the SiC substrate.

Abstract: A semiconductor device of according to an embodiment of the present disclosure includes a n-type SiC layer; a SiC region provided on the n-type SiC layer and containing H (hydrogen) or D (deuterium) in an amount of 1×1018 cm?3 or more and 1×1022 cm?3 or less; and a metal layer provided on the SiC region.

Abstract: According to one embodiment, a semiconductor device includes a structure, an insulating film, a control electrode, first and second electrodes. The structure has a first surface, and includes a first, a second, and a third semiconductor region. The structure has a portion including the first, second, and third semiconductor regions arranged in a first direction along the first surface. The insulating film is provided on the first surface. The control electrode is provided on the insulating film. The first electrode is electrically connected to the third semiconductor region. The second electrode is electrically connected to the first semiconductor region. The insulating film includes a charge trap region. A bias voltage is applied to the first and second electrodes, and includes a shift voltage. The shift voltage shifts a reference potential of a voltage applied to the first and second electrodes by a certain voltage.

Abstract: A semiconductor device manufacturing method according to an embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.

Abstract: A semiconductor device according to an embodiment includes a SiC semiconductor layer, a gate electrode, a gate insulating film provided between the SiC semiconductor layer and the gate electrode, and a region that is provided between the SiC semiconductor layer and the gate insulating film and includes at least one element selected from the group consisting of antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), and lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu). The concentration of the at least one element is equal to or greater than 1×1019 cm?3 and equal to or less than 2.4×1022 cm?3.

Abstract: A semiconductor device of an embodiment includes a p-type SiC layer; a SiC region provided on the p-type SiC layer and containing H (hydrogen) or D (deuterium) in an amount of 1×1018 cm?3 or more and 1×1022 cm?3 or less; and a metal layer provided on the SiC region.

Abstract: A semiconductor device according to embodiments includes a p-type SiC region, a gate insulating film disposed on the p-type SiC region, and a gate electrode disposed on the gate insulating film and including a p-type impurity and 3C-SiC.

Abstract: A semiconductor device according to an embodiment includes a first metal layer, a second metal layer, an n-type first SiC region provided between the first metal layer and the second metal layer and having an n-type impurity concentration of 1×1018 cm?3 or less, and a conductive layer provided between the first SiC region and the first metal layer and containing titanium (Ti), oxygen (O), and at least one element selected from the group consisting of vanadium (V), niobium (Nb), and tantalum (Ta).

Abstract: An electric power conversion device of an embodiment includes the electric power conversion device expressed as an equivalent circuit including, a power supply, a first parasitic inductance, a first diode; a second parasitic inductance connected to the first diode in series, a second diode connected to the first diode in parallel, a third parasitic inductance connected to the second diode in series, a switching element, a gate circuit, and a load. The equivalent circuit includes a first circuit loop and a second circuit loop. The first circuit loop includes the power supply, the first parasitic inductance, the first diode, the second parasitic inductance, the switching element, and the gate circuit. The second circuit loop includes the power supply, the first parasitic inductance, the second diode, the third parasitic inductance, the switching element, and the gate circuit.

Abstract: A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; an n-type SiC layer provided on one side of the semiconductor substrate; a p-type first SiC region provided in the n-type SiC layer; a metallic second SiC region provided in the p-type first SiC region, the second SiC region containing at least one element selected from the group of Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid; a gate electrode; a gate insulating film provided between the gate electrode and the n-type SiC layer, the gate insulating film provided between the gate electrode and the first SiC region; a first electrode provided on the second SiC region; and a second electrode provided on a side of the semiconductor substrate opposite to the n-type SiC layer.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The first semiconductor region includes silicon carbide. A conductivity type of the first semiconductor region is a first conductivity type. The second semiconductor region includes silicon carbide. A conductivity type of the second semiconductor region is a second conductivity type. The third semiconductor region includes silicon carbide. A conductivity type of the third semiconductor is the second conductivity type. The third semiconductor region is provided between the first semiconductor region and the second semiconductor region. As viewed in a direction connecting the first semiconductor region and the second semiconductor region, an area of an overlapping region of the second semiconductor region and the third semiconductor region is smaller than an area of an overlapping region of the first semiconductor region and the second semiconductor region.

Abstract: A semiconductor device according to an embodiment includes a SiC layer including a first region provided at a surface. The first region satisfies NA?ND<5×1015 cm?3 when a concentration of a p-type impurity is denoted by NA, whereas a concentration of an n-type impurity is denoted by ND. The surface is inclined at 0 degrees or more and 10 degrees or less to a {000-1} face, or the surface having a normal direction inclined at 80 degrees or more and 90 degrees or less to a <000-1> direction. The device includes a gate electrode, a gate insulating film provided between the SiC layer and the gate electrode, and a second region provided between the first region and the gate insulating film. The second region has a nitrogen concentration higher than 1×1022 cm?3.

Abstract: The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method.

Abstract: An electric power conversion device of an embodiment includes the electric power conversion device expressed as an equivalent circuit including, a power supply, a first parasitic inductance, a first diode; a second parasitic inductance connected to the first diode in series, a second diode connected to the first diode in parallel, a third parasitic inductance connected to the second diode in series, a switching element, a gate circuit, and a load. The equivalent circuit includes a first circuit loop and a second circuit loop. The first circuit loop includes the power supply, the first parasitic inductance, the first diode, the second parasitic inductance, the switching element, and the gate circuit. The second circuit loop includes the power supply, the first parasitic inductance, the second diode, the third parasitic inductance, the switching element, and the gate circuit.

Abstract: A semiconductor device of an embodiment includes, an n-type SiC substrate that has first and second faces, and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus), the ratio of the concentration of the element A to the concentration of the element D in the combination(s) being higher than 0.40 but lower than 0.95, the concentration of the element D forming the combination(s) being not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3, an SiC layer formed on the first face, a first electrode formed on the first face side, and a second electrode formed on the second face.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first electrode, a second electrode, a control electrode and an insulating film. The first semiconductor region is of a first conductivity type and includes SiC. The second semiconductor region is provided on the first semiconductor region and has a first surface. The second semiconductor region is of a second conductivity type and includes SiC. The third semiconductor region is provided on the second semiconductor region, is of the first conductivity type and includes SiC. The first and second electrodes are electrically connected to the third semiconductor region. The control electrode is provided on the second semiconductor region. The insulating film is provided between the second semiconductor region and the control electrode. The insulating film contacts the first surface and the control electrode and includes nitrogen.

Abstract: A semiconductor device of the embodiment includes an SiC layer of 4H-SiC structure having a surface inclined at an angle from 0 degree to 30 degrees relative to {11-20} face or {1-100} face, a gate electrode, a gate insulating film provided between the surface and the gate electrode, a n-type first SiC region provided in the SiC layer, a n-type second SiC region provided in the SiC layer, a channel forming region provided in the SiC layer between the first SiC region and the second SiC region, the channel forming region provided adjacent to the surface, and the channel forming region having a direction inclined at an angle from 60 degrees to 90 degrees relative to a <0001> direction or a <000-1> direction.