Abstract: A control system for a secondary battery which is less affected by the ambient temperature by performing temperature control of the secondary battery is provided. A control system for a secondary battery which is less affected by the ambient temperature and in which a plurality of kinds of secondary batteries are used for temperature control is achieved and mounted on a vehicle. Specifically, when the ambient temperature is low, some of second secondary batteries are heated by self-heating of a first secondary battery. After the second secondary batteries are sufficiently heated, the rest of the second secondary batteries are heated in stages by self-heating of the some of the second secondary batteries whose temperature has been increased.

Abstract: A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.

Abstract: An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.

Abstract: An imaging device having a function of processing an image is provided. The imaging device has an additional function such as image processing, can hold analog data obtained by an image capturing operation in a pixel, and can extract data obtained by multiplying the analog data by a predetermined weight coefficient. Difference data between adjacent light-receiving devices can be obtained in a pixel, and data on luminance gradient can be obtained. When the data is taken in a neural network or the like, inference of distance data or the like can be performed. Since enormous volume of image data in the state of analog data can be held in pixels, processing can be performed efficiently.

Abstract: A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and/or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.

Abstract: A battery management circuit, a battery protection circuit, a power storage device, a semiconductor device, a vehicle, and an electronic device, or the like with a novel structure, a low power consumption structure, or a highly integrated structure is provided. The semiconductor device includes a first transistor comprising a first conductor and a first semiconductor over the first conductor, a first insulator over the first transistor, a second conductor provided in an opening of the first insulator, a second transistor over the first insulator, and a third conductor over the second transistor. The first conductor has a function of one of a source electrode and a drain electrode of the first transistor. The first semiconductor and the second conductor overlap each other. The second conductor and the third conductor overlap each other. The third conductor and the second transistor overlap each other.

Abstract: A small-sized and highly functional imaging device is provided. The imaging device includes a photoelectric conversion device formed on a silicon substrate and a transistor including a channel formation region in a silicon epitaxial growth layer formed on the silicon substrate. The transistor provided in the epitaxial growth layer has favorable electrical characteristics, so that the imaging device with little noise can be formed. Since the transistor can be formed so as to have a region overlapping with the photoelectric conversion device, the imaging device can be downsized.

Abstract: An imaging apparatus including a light source is provided. The imaging apparatus includes a light-emitting device and a photoelectric conversion device in a pixel, and a pixel circuit has a function of outputting third data generated by multiplying obtained first data by second data (weight). Calculating the third data externally enables more detailed information on a subject with respect to a specific wavelength to be obtained. In addition, reading out collectively a plurality of pixels to which proper weight is given enables output of difference data between pixels and the like, which allows external calculation to be omitted.

Abstract: An imaging device capable of image processing is provided. The imaging device has an image recognition function. In the imaging device, cells have a function of acquiring imaging data and a function of retaining weight data. Among the cells arranged in a matrix, some of the cells acquire imaging data and the rest of the cells retain weight data. Then, arithmetic operation is performed using the imaging data and the weight data. For example, all the imaging data can be subjected to arithmetic operation where products of the imaging data and the weight data are calculated and the sum of the calculated products is calculated. That is, product-sum operation can be performed. When an arithmetic operation result is captured by a neural network such as a convolutional neural network (CNN) or the like, the additional function can be used because image processing can be performed on the imaging data.

Abstract: A neural network circuit having a novel structure is provided. A plurality of arithmetic circuits each including a register, a memory, a multiplier circuit, and an adder circuit are provided. The memory outputs different weight data in response to switching of a context signal. The multiplier circuit outputs multiplication data of the weight data and input data held in the register. The adder circuit performs a product-sum operation by adding the obtained multiplication data to data obtained by a product-sum operation in an adder circuit of another arithmetic circuit. The obtained product-sum operation data is output to an adder circuit of another arithmetic circuit, so that product-sum operations of different weight data and input data are performed.

Abstract: A high-definition display device is provided. A small display device is provided. In the display device, a first layer and a second layer are stacked and provided. The first layer includes a gate driver circuit and a source driver circuit, and the second layer includes a display portion. The gate driver circuit and the source driver circuit are provided to include a region overlapping with the display portion. The gate driver circuit and the source driver circuit have an overlap region where they are not strictly separated from each other. Five or more gate driver circuits and five or more source driver circuits can be provided.

Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.

Abstract: A data device with a small circuit area and reduced power consumption is used. The data processing device includes a NAND memory portion and a controller. The memory portion includes a first string and a second string in different blocks. The first string includes a first memory cell, and the second string includes a second memory cell. On reception of first data and a signal including an instruction to write the first data, the controller writes the first data to the first memory cell. Then, the controller reads the first data from the first memory cell and writes the first data to the second memory cell.

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a memory circuit including a first transistor and a second transistor. The first transistor is formed on a silicon substrate. The second transistor is formed in a layer above a layer where the first transistor is provided. The first transistor includes a first gate electrode and a first back gate electrode with a first channel formation region interposed therebetween. The first gate electrode is electrically connected to one of a source and a drain of the second transistor. The first back gate electrode is formed using a region where an impurity element imparting a conductivity type is selectively introduced in the silicon substrate. The second transistor includes a second channel formation region. The second channel formation region includes a metal oxide.

Abstract: A novel functional panel that is highly convenient or highly reliable is provided. The functional panel includes a first pixel. The first pixel includes a first element, a color conversion layer, and a first functional layer. The first functional layer is positioned between the first element and the color conversion layer. The first element has a function of emitting light and contains gallium nitride. The color conversion layer has a function of converting the color of light emitted from the first element into a different color. The first functional layer includes a first insulating film and a pixel circuit. The first insulating film includes a region positioned between the pixel circuit and the first element, and has an opening. The pixel circuit includes a first transistor. The first transistor includes a first oxide semiconductor film and is electrically connected to the first element through the opening.

Abstract: A display apparatus with a high level of immersion or realistic sensation is provided. The display apparatus includes a display portion capable of full-color display, a communication portion having a wireless communication function, and a wearing portion that can be worn on a head. In an emission spectrum of blue display provided by the display portion at a first luminance, when the intensity of a first emission peak at a wavelength higher than or equal to 400 nm and lower than 500 nm is 1, the intensity of a second emission peak at a wavelength higher than or equal to 500 nm and lower than or equal to 700 nm in the emission spectrum is 0.5 or lower. The first luminance is any value higher than 0 cd/m2 and lower than 1 cd/m2.

Abstract: An imaging panel is provided. The imaging panel includes a photoelectric conversion element, a pixel, a first conductive film, a second conductive film, a third conductive film, a fourth conductive film, and a fifth conductive film. The pixel includes a pixel circuit and supplies an image signal. The first conductive film is supplied with the image signal and the photoelectric conversion element includes a first terminal connected to the second conductive film and a second terminal connected to the pixel circuit. The pixel circuit includes a first switch, a second switch, a third switch, a transistor, and a capacitor. The first switch includes a terminal connected to the second terminal of the photoelectric conversion element and a terminal connected to a node. The transistor includes a gate electrode connected to the node and a first electrode connected to the third conductive film.

Abstract: A display device in which a pixel defect is less likely to be perceived is provided. The display device includes a display portion where pixels are arranged in a matrix, and a sensor portion including a photoelectric conversion element. First, the display portion is divided into a first region and a second region. Next, first light is emitted from the pixel included in the first region, and the luminance of the first light is detected by the photoelectric conversion element. Moreover, second light is emitted from the pixel included in the second region, and the luminance of the second light is detected by the photoelectric conversion element. Then, the luminance of the first light is compared to the luminance of the second light, and on the basis of the comparison result, one of the first region and the second region is divided into a third region and a fourth region. By repeating these operations, a defective pixel is detected.

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a p-channel transistor and an n-channel transistor provided over a silicon substrate. One of a source and a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source and a drain of the n-channel transistor is electrically connected to a second power supply line, and the other of the source and the drain of the p-channel transistor is connected to the other of the source and the drain of the n-channel transistor. The p-channel transistor includes a first gate electrode and a first back gate electrode provided to face the first gate electrode with a first channel formation region therebetween. The first back gate electrode is formed using a region where an impurity element imparting conductivity is selectively introduced to the silicon substrate. The n-channel transistor is provided above a layer including the p-channel transistor.

Abstract: A low-power memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cache memory are connected to each other with a short wiring, and signal transmission delay is small is provided. For example, the NAND flash memory is formed using a Si transistor formed with a single crystal silicon substrate. Since an OS transistor can be formed by a method such as a thin-film method, the cache memory formed using the OS memory can be stacked over the NAND flash memory. When the NAND flash memory and the cache memory are formed in one chip, the NAND flash memory and the controller can be connected to each other with a short wiring, and the controller and the cache memory can be connected to each other with a short wiring.