Patents by Inventor Takeshi Hamamoto
Takeshi Hamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7952162Abstract: A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.Type: GrantFiled: August 14, 2009Date of Patent: May 31, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Hamamoto
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Publication number: 20110062504Abstract: An aspect of the present disclosure, there is provided semiconductor memory device including a ferroelectric capacitor and a field effect transistor as a memory cell, the ferroelectric capacitor including a lower electrode connected to one of the pair of the impurity diffusion layers, a bit line formed below the lower electrode, wherein each of the memory cells shares the bit line contact with an adjacent memory cell at one side in the first direction to connect to the bit line, and three of the word lines are formed between the bit line contacts in the first direction.Type: ApplicationFiled: March 10, 2010Publication date: March 17, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi HAMAMOTO
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Patent number: 7811878Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.Type: GrantFiled: April 14, 2009Date of Patent: October 12, 2010Assignees: Sumco Corporation, Kabushiki Kaisha ToshibaInventors: Tetsuya Nakai, Bong-Gyun Ko, Takeshi Hamamoto, Takashi Yamada
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Publication number: 20100190304Abstract: A semiconductor storage device, has a first conductive type semiconductor region formed on a semiconductor substrate, a plurality of second conductive type semiconductor regions formed separately from each other on the first conductive type semiconductor region, a plurality of MOSFETs each formed on the plurality of second conductive type semiconductor regions, and element isolating regions each formed between the adjacent second conductive type semiconductor regions, a bottom surface of which being located in the first conductive type semiconductor region, wherein the number of crystal defects per unit volume in the first conductive type semiconductor region is larger than the number of the crystal defects per unit volume in the second conductive type semiconductor regions.Type: ApplicationFiled: April 1, 2010Publication date: July 29, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi HAMAMOTO
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Publication number: 20100181622Abstract: A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.Type: ApplicationFiled: August 14, 2009Publication date: July 22, 2010Applicant: Kabushiki Kaisha ToshibaInventor: Takeshi HAMAMOTO
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Patent number: 7759255Abstract: In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity.Type: GrantFiled: November 20, 2006Date of Patent: July 20, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Hamamoto, Akihiro Nitayama
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Patent number: 7732271Abstract: According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate beloType: GrantFiled: August 4, 2008Date of Patent: June 8, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Hamamoto, Akihiro Nitayama
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Patent number: 7719056Abstract: This disclosure concerns a method of manufacturing a semiconductor memory device comprising forming a plurality of trenches in a semiconductor substrate; forming a semiconductor layer provided on a cavity by connecting lower spaces of the trenches to one another and closing upper openings of the trenches in a heat treatment under a hydrogen atmosphere; etching the semiconductor layer in an isolation formation area; forming an insulating film on a side surface and a bottom surface of the semiconductor layer; filling the cavity under the semiconductor layer with an electrode material; and forming a memory element on the semiconductor layer.Type: GrantFiled: March 16, 2007Date of Patent: May 18, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Hamamoto
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Publication number: 20100115765Abstract: The layout verification apparatus includes: a verification unit for obtaining mask data indicating a mask pattern to be drawn on a mask based on layout and wiring data indicating positions of a group of primitive cells and positions of connection wires connected to the group of primitive cells, and for verifying a position of the mask pattern based on the mask data, so as to detect an error part; and a correction hint creating unit for creating correction hint information based on the error part, and for sending the correction hint information to a layout and wiring unit for correcting the layout and wiring data. The correction hint creating unit obtains terminal information indicating positions of a group of terminals included in the group of primitive cells and creates the correction hint information based on the terminal information so that the positions of the group of terminals are not changed by the layout and wiring unit.Type: ApplicationFiled: September 15, 2009Publication date: May 13, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Takeshi Hamamoto
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Patent number: 7692963Abstract: The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.Type: GrantFiled: November 2, 2007Date of Patent: April 6, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Shino, Akihiro Nitayama, Takeshi Hamamoto, Hideaki Aochi, Takashi Ohsawa, Ryo Fukuda
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Publication number: 20100019304Abstract: A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.Type: ApplicationFiled: July 2, 2009Publication date: January 28, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiro MINAMI, Takashi Ohsawa, Tomoaki Shino, Takeshi Hamamoto, Akihiro Nitayama
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Patent number: 7609551Abstract: This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.Type: GrantFiled: September 25, 2007Date of Patent: October 27, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Shino, Akihiro Nitayama, Takeshi Hamamoto, Hideaki Aochi, Takashi Ohsawa, Ryo Fukuda
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Publication number: 20090203187Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.Type: ApplicationFiled: April 14, 2009Publication date: August 13, 2009Applicants: SUMCO CORPORATION, KABUSHIKI KAISHA TOSHIBAInventors: Tetsuya NAKAI, Bong-Gyun KO, Takeshi HAMAMOTO, Takashi YAMADA
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Publication number: 20090152610Abstract: This disclosure concerns a semiconductor memory device including bit lines; word lines; semiconductor layers arranged to correspond to crosspoints of the bit lines and the word lines; bit line contacts connecting between a first surface region and the bit lines, the first surface region being a part of a surface region of the semiconductor layers directed to the word lines and the bit lines; and a word-line insulating film formed on a second surface region adjacent to the first surface region, the second surface region being a part of out of the surface region, the word-line insulating film electrically insulating the semiconductor layer and the word line, wherein the semiconductor layer, the word line and the word-line insulating film form a capacitor, and when a potential difference is given between the word line and the bit line, the word-line insulating film is broken in order to store data.Type: ApplicationFiled: December 11, 2008Publication date: June 18, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiro Minami, Ryo Fukuda, Takeshi Hamamoto
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Patent number: 7537989Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form a buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.Type: GrantFiled: November 13, 2006Date of Patent: May 26, 2009Assignees: Sumco Corporation, Kabushiki Kaisha ToshibaInventors: Tetsuya Nakai, Bong-Gyun Ko, Takeshi Hamamoto, Takashi Yamada
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Publication number: 20090114989Abstract: This disclosure concerns a semiconductor memory device including a semiconductor substrate; a buried insulation film provided on the semiconductor substrate; a semiconductor layer provided on the buried insulation film; a source layer and a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer, and being in an electrically floating state, the body region accumulating or discharging charges to store data; a gate dielectric film provided on the body region; a gate electrode provided on the gate dielectric film; and a plate electrode facing a side surface of the body region via an insulation film, in an element isolation region.Type: ApplicationFiled: November 3, 2008Publication date: May 7, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi HAMAMOTO
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Publication number: 20080305588Abstract: According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate beloType: ApplicationFiled: August 4, 2008Publication date: December 11, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi Hamamoto, Akihiro Nitayama
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Publication number: 20080251142Abstract: In a miniflow valve which is disposed in a miniflow pipe that is connected between the discharge side and suction side of a main pipe where a liquid fed under pressure by a centrifugal pump circulates, and which is opened when the head of the centrifugal pump has exceeded a predetermined value, thereby to return a fluid from the discharge side onto the suction side through the miniflow pipe; a miniflow valve including a pilot valve which is opened or closed on the basis of the differential pressure between the discharge side pressure and suction side pressure of the liquid, and a main valve which is opened or closed in accordance with the opening or closing operation of the pilot valve. The miniflow valve has the simple configuration, and can be opened or closed at a high precision.Type: ApplicationFiled: April 9, 2008Publication date: October 16, 2008Inventors: Shinji OGINO, Takeshi HAMAMOTO
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Publication number: 20080239789Abstract: The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.Type: ApplicationFiled: November 2, 2007Publication date: October 2, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tomoaki SHINO, Akihiro Nitayama, Takeshi Hamamoto, Hideaki Aochi, Takashi Ohsawa, Ryo Fukuda
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Publication number: 20080242048Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.Type: ApplicationFiled: November 13, 2006Publication date: October 2, 2008Applicants: SUMCO CORPORATION, TOSHIBA CORPORATIONInventors: Tetsuya Nakai, Bong Gyun Ko, Takeshi Hamamoto, Takashi Yamada