Abstract: A sense amplifier driving line is connected to the source of an N-channel MOS transistor. Accordingly, even if a control signal attains H level, a sub-amplifier will not operate. This is because the sense amplifier driving line and an LIO line pair both attain a precharge potential, and a gate-source voltage of an N-channel MOS transistor attains 0V. Thus, it is not necessary to add a circuit configuration for supplying a signal notifying of activation of a row block, and a semiconductor memory device with a smaller area is obtained.

Abstract: Data indicating whether a short-circuit defect exists in a memory block is programmed a fuse program circuit. In accordance with the fuse program data and a mode instruction signal, the correspondence relationship between a block select signal and a corresponding bit line isolation instruction signal is switched by a circuit that generates the bit line isolation instruction signal in a specific mode. It becomes possible to isolate the memory block in which a leakage current path exists from a corresponding sense amplifier band in a specific operation mode. Current consumption at least at a standby state is reduced.

Abstract: A clock signal, which is generated by utilizing a delay circuit having a delay time depending on the operation frequency of an internal clock signal, is applied to a first circuit for activation thereof, and a clock signal, which has a fixed delay not dependent on the clock frequency and is adjusted in phase with respect to an external clock signal, is applied to a second circuit receiving the output signal of the first circuit for operation thereof. Thus, the operation timing of the second circuit can be set to be as late as possible. Consequently, it is possible to mitigate the operation conditions of the first circuit, to achieve a high speed data transfer. Even in the high speed operation, internal data can be reliably taken in, and transferred accurately.

Abstract: An array power generation circuit supplying an array power supply voltage to a corresponding memory array block and a peripheral power generation circuit supplying a peripheral power supply voltage to a peripheral circuit are arranged around each memory array block. Respective power supply voltages are generated under the same reference voltage level, and transmitted in an array power supply line and a peripheral power supply line. An N channel MOS transistor is connected between the array power supply line of the array power generation circuit and the peripheral power supply line of the peripheral power generation circuit. The N channel MOS transistor is turned on when the gate thereof receives a boosted voltage from a booster circuit, and electrically couples the array power supply line and the peripheral power supply line.

Abstract: An estimated pattern for forming a mask is divided into rectangles, a selected region is selected from the pattern, and, when a minute shape is present in the selected region, the selected region is redivided into a plurality of rectangles. The selected region is a region in which a gate electrode of a transistor, a contact, or a via hole is formed.

Abstract: An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential 1/2 times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.

Abstract: The internal power-supply potential generating circuit includes a reference potential generating circuit having small dependency on an external power-supply potential and on a temperature, an MOS transistor for pull up, a level shifter producing a potential lower than a reference potential by a prescribed voltage to a first node and producing a potential lower than an internal power-supply potential by a voltage of the sum of the prescribed potential and an offset potential to a second node, and a differential amplifier bringing an MOS transistor out of conduction in response to the potential of the second node reaching the potential of the first node. Thus, the reference potential may be set lower by the offset voltage, allowing stable reference potential and internal power-supply potential to be obtained even if the external power-supply potential is lowered.

Abstract: The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.

Abstract: Complementary signals on a pair of first signal lines are transferred onto a pair of second signal lines in synchronization with a clock signal by a buffer circuit. The buffer circuit includes an equalize circuit to equalize a pair of internal nodes to a prescribed potential, a transfer gate circuit activated, when the equalize circuit completes equalization, to couple the pair of first signal lines and the pair of internal nodes, an amplifier circuit to differentially amplify the signals on the internal nodes when the transfer gate completes the transfer operation, an output transfer circuit to transmit the signals on the pair of internal nodes onto the pair of second signal lines in synchronization with the clock signal, and a control circuit to control the operation of the equalize circuit, the transfer gate circuit and the amplifier circuit. After the pair of internal nodes is equalized to the prescribed potential, the signals from the pair of first signal lines are received and amplified.

Abstract: A semiconductor memory device wherein, if an address-input buffer section 3 is arranged away from a central part of a memory chip 8, then a second address-latch circuit section 5 is arranged at a neighborhood of the address-input buffer section 3. By this means, the deterioration of the setup/hold characteristics in the address data IA[0-12] of the internal address signal due to coupling noise between wiring lines and the like can be prevented. A first address-latch circuit section 4 is arranged at a central part of the memory chip 8, so that delays in a bank-control signal for memory banks 2a to 2d and the like can be prevented.

Abstract: An optical proximity effect correcting method in a semiconductor manufacturing process includes adding, detecting, judging, and deleting. The adding includes adding a first correcting region around a portion of a first design pattern. The portion faces a second design pattern. A first corrected design pattern includes the first correcting region and the first design pattern. The detecting includes detecting a space between the first corrected design pattern and the second design pattern. The judging includes judging whether the space is smaller than or equal to a predetermined value. The deleting includes deleting at least a portion of the first correcting region such that the space is larger than the predetermined value, when the space is smaller than or equal to the predetermined value.

Abstract: A setting circuit provided at a central part of a chip to set a replacement address includes seven redundancy determining units, each of which includes a program set. Each of four banks are divided into half to provide the total of eight regions. Eight control buses are provided transmitting data corresponding to the eight regions respectively. A bus determining unit selects a corresponding control bus in accordance with the contents of the program set and outputs replacement information. Therefore, each of the seven program sets can be used for replacement in any of the eight regions.

Abstract: A semiconductor memory device wherein, if an address-input buffer section 3 is arranged away from a central part of a memory chip 8, then a second address-latch circuit section 5 is arranged at a neighborhood of the address-input buffer section 3. By this means, the deterioration of the setup/hold characteristics in the address data IA[0-12] of the internal address signal due to coupling noise between wiring lines and the like can be prevented. A first address-latch circuit section 4 is arranged at a central part of the memory chip 8, so that delays in a bank-control signal for memory banks 2a to 2d and the like can be prevented.

Abstract: When an inputted column address CA and a defect address are compared with each other, an preset defect address and a defect conversion address obtained by inverse conversion of the defect address are both inputted to a comparison circuit. In the comparison circuit, coincidence determination operations are performed being switched between when address conversion is applied to the column address CA and when no address conversion is applied thereto, thereby coincidence comparison can be effected without using the column address CA after an address conversion operation; therefore, a delay in a determination operation accompanying a conversion operation is canceled to perform high speed data reading.

Abstract: In a semiconductor memory unit to which a plurality of different functions can be imparted by merely changing a portion of its production process, the improvement comprises: a plurality of data buses which include first data buses for use only in one of the functions and the remaining data buses for use in the one and the remainder of the functions; wherein when the semiconductor memory unit performs the remainder of the functions, the first data buses are utilized for the semiconductor memory unit.

Abstract: A semiconductor device is provided which avoids lowering of the sense speeds of plural sense amplifiers due to their drives. In the semiconductor device, a P-type well layer (6) containing a P-type impurity is selectively disposed in a main surface of an epitaxial layer (3). An N-type bottom layer (7) containing an N-type impurity is disposed so as to make contact with a bottom surface of the P-type well layer (6). A P-type well layer (2) is disposed in such a thickness as to make contact with the N-type bottom layer (7), so that the N-type bottom layer (7) and P-type well layer (2) form a PN junction. Further, in the main surface of the epitaxial layer (3), an N-type well layer (4) containing an N-type impurity and a P-type well layer (5) containing a P-type impurity are selectively disposed so as to sandwich therebetween the P-type well layer (6).

Abstract: MOS transistors are formed on island-shaped divided element regions of a silicon substrate, and provided with gate electrodes having the same widths as the element regions. Thereafter, capacitor grooves are formed at end portions of the element regions, and capacitor insulating films formed of BSTO are provided on inner walls of the capacitor grooves. Then, the capacitor grooves are filled with storage electrodes, thereby forming capacitors. Furthermore, connection conductors are formed to connect the storage electrodes and source diffusion layers of the MOS transistors. Then, word lines are formed to connect the gate electrodes of the MOS transistors, and further bit lines are formed to connect drain diffusion layers of the MOS transistors.

Abstract: A DDR SDRAM includes: an input buffer and a timing adjustment circuit for converting an external data strobe signal into a binary signal and adjusting the timing; a glitch elimination circuit for eliminating a glitch G′ from an output signal of the timing adjustment circuit to produce an internal data strobe signal; and an input buffer and a latch circuit for taking in a data signal in synchronization with the internal data strobe signal. Accordingly, even if an external data strobe signal suffers from a glitch, an internal circuit will not malfunction.

Abstract: An estimated pattern for forming a mask is divided into rectangles, a selected region is selected from the pattern, and, when a minute shape is present in the selected region, the selected region is redivided into a plurality of rectangles. The selected region is a region in which a gate electrode of a transistor, a contact, or a via hole is formed.

Abstract: A pattern density inspection apparatus is provided which improves the detection accuracy of a pattern data density error region, and outputs detection results for a designer to efficiently perform a correction operation without performing detection of pattern data density error regions which do not require correction. A control section 1 reads out layout data from a layout storage section 2, and stores this in an input processing section 3 and an output processing section 7. A data density computation processing section 4, while displacing layout data of the input processing section 3 from a position where pattern data was computed immediately before, in either one of an X axis direction and a Y axis direction, performs computations of the pattern density in the detection range after movement, and judges if the pattern data density is above 50%, and makes that above 50% a temporary error region.