Abstract: A semiconductor chip is provided with a phase comparison circuit (1), in addition to an integrated circuit implementing a normal operation. The phase comparison circuit (1) compares phases between an internal signal (A) of the integrated circuit and an external signal and outputs a monitor signal (MONSIG) expressing the result of this comparison outward from the semiconductor chip. Thus, the phase of the internal signal (A) of the integrated circuit can be directly detected.

Abstract: A silicide film is provided in diffusion regions formed in a semiconductor layer. The silicide film has a thickness substantially same as that of the semiconductor layer. The silicide film has the bottom located in the vicinity of an interface between the insulator film and the semiconductor layer.

Abstract: An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential ½ times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.

Abstract: At the time of burn-in test, substrate voltages of transistors in a sense amplifier are switched by a PMOS substrate voltage generating portion and an NMOS substrate voltage generating portion. Specifically, the substrate voltage of a P channel MOS transistor is increased during the test than in a normal operation, whereas the substrate voltage of an N channel MOS transistor is decreased during the test than in the normal operation. Consequently, the threshold voltages of the P channel and N channel MOS transistors can be increased upon the test. Leakage currents in the turned-off states can be reduced, and thus, power consumption during the burn-in test can be decreased.

Abstract: The PROM area is adjacent to the normal memory cell area. The data writing (normal writing) and the data reading (normal reading) for normal memory cell areas and the data writing (redundant writing) for the PROM area are carried out from the side of the normal memory cell areas. The data reading (redundant reading) for the PROM area is carried out from the side of the PROM area. In the PROM area, the PROM cells having the same structure as that of the normal memory cells are connected to the redundant sub bit lines. In the redundant writing, in the select gate area, the redundant sub bit lines and main bit lines are connected. In the redundant reading, in the redundant gate area having the same layout as that of the select gate area, the redundant sub bit lines are connected to redundant bit lines.

Abstract: A sense amplifier driving line is connected to the source of an N-channel MOS transistor. Accordingly, even if a control signal attains H level, a sub-amplifier will not operate. This is because the sense amplifier driving line and an LIO line pair both attain a precharge potential, and a gate-source voltage of an N-channel MOS transistor attains 0V. Thus, it is not necessary to add a circuit configuration for supplying a signal notifying of activation of a row block, and a semiconductor memory device with a smaller area is obtained.

Abstract: A semiconductor chip is provided with a phase comparison circuit (1), in addition to an integrated circuit implementing a normal operation. The phase comparison circuit (1) compares phases between an internal signal (A) of the integrated circuit and an external signal and outputs a monitor signal (MONSIG) expressing the result of this comparison outward from the semiconductor chip. Thus, the phase of the internal signal (A) of the integrated circuit can be directly detected.

Abstract: An insulated gate type field effect transistor in a memory cell array is a transistor having a gate insulating film which is thicker than a gate insulating film of an insulated gate type field effect transistor in an array peripheral circuit. DRAM (Dynamic Random Access Memory) cell-based semiconductor memory device can be implemented which allows a burn-in test to be accurately performed without degrading sensing operation characteristics even under a low power supply voltage.

Abstract: A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

Abstract: Data indicating whether a short-circuit defect exists in a memory block is programmed a fuse program circuit. In accordance with the fuse program data and a mode instruction signal, the correspondence relationship between a block select signal and a corresponding bit line isolation instruction signal is switched by a circuit that generates the bit line isolation instruction signal in a specific mode. It becomes possible to isolate the memory block in which a leakage current path exists from a corresponding sense amplifier band in a specific operation mode. Current consumption at least at a standby state is reduced.

Abstract: An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential 1/2 times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.

Abstract: A semiconductor chip is provided with a phase comparison circuit (1), in addition to an integrated circuit implementing a normal operation. The phase comparison circuit (1) compares phases between an internal signal (A) of the integrated circuit and an external signal and outputs a monitor signal (MONSIG) expressing the result of this comparison outward from the semiconductor chip. Thus, the phase of the internal signal (A) of the integrated circuit can be directly detected.

Abstract: A semiconductor device is provided which avoids lowering of the sense speeds of plural sense amplifiers due to their drives. In the semiconductor device, a P-type well layer (6) containing a P-type impurity is selectively disposed in a main surface of an epitaxial layer (3). An N-type bottom layer (7) containing an N-type impurity is disposed so as to make contact with a bottom surface of the P-type well layer (6). A P-type well layer (2) is disposed in such a thickness as to make contact with the N-type bottom layer (7), so that the N-type bottom layer (7) and P-type well layer (2) form a PN junction. Further, in the main surface of the epitaxial layer (3), an N-type well layer (4) containing an N-type impurity and a P-type well layer (5) containing a P-type impurity are selectively disposed so as to sandwich therebetween the P-type well layer (6).

Abstract: An array power generation circuit supplying an array power supply voltage to a corresponding memory array block and a peripheral power generation circuit supplying a peripheral power supply voltage to a peripheral circuit are arranged around each memory array block. Respective power supply voltages are generated under the same reference voltage level, and transmitted in an array power supply line and a peripheral power supply line. An N channel MOS transistor is connected between the array power supply line of the array power generation circuit and the peripheral power supply line of the peripheral power generation circuit. The N channel MOS transistor is turned on when the gate thereof receives a boosted voltage from a booster circuit, and electrically couples the array power supply line and the peripheral power supply line.

Abstract: In the semiconductor memory device, a control circuit generates various commands for a memory cell array according to an internal command control signal and an internal address signal output from an input switching circuit for switching an input source of the command control signals and the address signal between an external terminal and a BIST circuit. In the BIST mode, the input switching circuit cuts the signal input from the external terminal and generates the internal command control signal and the internal address signal according to an output signal from the BIST circuit. Transition to the BIST mode and return to the normal operation mode are indicated by a combination of signals supplied to the external terminal. Therefore, an interface between a built in BIST circuit and other internal circuits can be secured without an addition of a special interface specification.

Abstract: The semiconductor memory device has a formal mode and a test mode as operating modes. The program circuit includes a fuse element in which an address using a spare memory cell instead of a defective memory cell is programmed. The program circuit confirms a disconnection state of a fuse in a condition severer in the test mode than that in the normal mode. An anomaly is notified to outside by a detection circuit in a case where results are different between the test mode and the normal mode. In a case where a fuse is not completely blown, such a fuse can also be detected in the test mode to exclude a defective chip.

Abstract: An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential 1/2 times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.

Abstract: The internal power-supply potential generating circuit includes a reference potential generating circuit having small dependency on an external power-supply potential and on a temperature, an MOS transistor for pull up, a level shifter producing a potential lower than a reference potential by a prescribed voltage to a first node and producing a potential lower than an internal power-supply potential by a voltage of the sum of the prescribed potential and an offset potential to a second node, and a differential amplifier bringing an MOS transistor out of conduction in response to the potential of the second node reaching the potential of the first node. Thus, the reference potential may be set lower by the offset voltage, allowing stable reference potential and internal power-supply potential to be obtained even if the external power-supply potential is lowered.

Abstract: A semiconductor device includes two sense amplifiers provided on a semiconductor substrate. Each of two sense amplifiers is formed of a pair of transistors. Two transistors are separated from each other by an element-isolating insulating portion provided on the semiconductor substrate. Therefore unlike the conventional, two transistors do not share the source region with each other, resulting in a semiconductor device with an improved sensitivity of a sense amplifier.

Abstract: At the time of burn-in test, substrate voltages of transistors in a sense amplifier are switched by a PMOS substrate voltage generating portion and an NMOS substrate voltage generating portion. Specifically, the substrate voltage of a P channel MOS transistor is increased during the test than in a normal operation, whereas the substrate voltage of an N channel MOS transistor is decreased during the test than in the normal operation. Consequently, the threshold voltages of the P channel and N channel MOS transistors can be increased upon the test. Leakage currents in the turned-off states can be reduced, and thus, power consumption during the burn-in test can be decreased.