Abstract: A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on-resistance while maintaining a high breakdown voltage. The semiconductor device includes a semiconductive substrate region, through which a current flows in the ON-state of the device and that is depleted in the OFF-state. The semiconductive substrate region includes a plurality of vertical alignments of n-type buried regions 32 and a plurality of vertical alignments of p-type buried regions. The vertically aligned n-type buried regions and the vertically aligned p-type buried regions are alternately arranged horizontally. The n-type buried regions and p-type buried regions are formed by diffusing respective impurities into highly resistive n-type layers 32a laminated one by one epitaxially.

Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Abstract: A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on- resistance while maintaining a high breakdown voltage. The semiconductor device includes a semiconductive substrate region, through which a current flows in the ON-state of the device and that is depleted in the OFF-state. The semiconductive substrate region includes a plurality of vertical alignments of n-type buried regions 32 and a plurality of vertical alignments of p-type buried regions. The vertically aligned n-type buried regions and the vertically aligned p-type buried regions are alternately arranged horizontally. The n-type buried regions and p-type buried regions are formed by diffusing respective impurities into highly resistive n-type layers 32a laminated one by one epitaxially.

Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least {fraction (1/100)} of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.

Abstract: A MOS semiconductor device includes n?-type surface regions, which are extended portions of an n?-type drift layer 12 extended to the surface of the semiconductor chip. Each n?-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n?-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 ?m or less.

Abstract: A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

Abstract: A semiconductor device includes an improved drain drift layer structure of alternating conductivity types, that is easy to manufacture, and that facilitates realizing a high current capacity and a high breakdown voltage and to provide a method of manufacturing the semiconductor device. The vertical MOSFET according to the invention includes an alternating-conductivity-type drain drift layer on an n+-type drain layer as a substrate. The alternating-conductivity-type drain drift layer is formed of n-type drift current path regions and p-type partition regions alternately arranged laterally with each other. The n-type drift current path regions and p-type partition regions extend in perpendicular to n+-type drain layer. Each p-type partition region is formed by vertically connecting p-type buried diffusion unit regions Up. The n-type drift current path regions are residual regions, left after connecting p-type buried diffusion unit regions Up, with the conductivity type thereof unchanged.

Abstract: A MOS semiconductor device includes n?-type surface regions, which are extended portions of an n?-type drift layer 12 extended to the surface of the semiconductor chip. Each n?-type surface region 14 is shaped with a stripe surrounded by a p-type well region. The surface area ratio between n?-type surface regions 14 and p-type well region 13 including an n+-type region 15 is from 0.01 to 0.2. The MOS semiconductor device further includes, in the breakdown withstanding region thereof, a plurality of guard rings, the number of which is equal to or more than the number n calculated from the following equation n=(Breakdown voltage Vbr (V))/100, and the spacing between the adjacent guard rings is set at 1 ?m or less.

Abstract: A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.

Abstract: A high breakdown voltage junction terminating structure having a loop-like RESURF structure formed on a SOI substrate is disclosed. A lateral IGBT, a lateral FWD, an output stage element and a driving circuit are formed in the inside region of the structure. The lateral IGBT and the lateral FWD are surrounded by a trench isolation region as an insulation region. Drain electrodes of high breakdown voltage NMOSFETs are provided on the inside of the high breakdown voltage junction terminating structure. Along with this, a gate electrode and a source electrode of each of the NMOSFETs are provided on the outside of the high breakdown voltage junction terminating structure. The periphery of the high breakdown voltage junction terminating structure is surrounded by a trench isolation region as a second insulation region. A control circuit is provided on the outside of the second insulation region.

Abstract: A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on-resistance while maintaining a high breakdown voltage. The semiconductor device includes a semiconductive substrate region, through which a current flows in the ON-state of the device and that is depleted in the OFF-state. The semiconductive substrate region includes a plurality of vertical alignments of n-type buried regions 32 and a plurality of vertical alignments of p-type buried regions. The vertically aligned n-type buried regions and the vertically aligned p-type buried regions are alternately arranged horizontally. The n-type buried regions and p-type buried regions are formed by diffusing respective impurities into highly resistive n-type layers 32a laminated one by one epitaxially.

Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.

Abstract: A semiconductor device for use in includes a base and emitter shorted by means of a surface electrode. The surface electrode of a vertical-type bipolar transistor in which a P-type epitaxial growth layer and a P-type semiconductor substrate form the collector is electrically connected to the drain electrode of a lateral MOSFET by means of a metal electrode wiring. Upon application of a high ESD voltage and high surge voltage, the energy of the ESD and surge is absorbed by operation of the vertical-type bipolar transistor and is limited to a voltage equal to or less than the breakdown voltage of the lateral MOSFET that was to be destroyed.

Abstract: A semiconductor device has an alternating conductivity type layer that improves the tradeoff relation between the ON-resistance and the breakdown voltage and a method of manufacturing such a semiconductor device. The alternating conductivity type layer is formed of n-type drift regions and p-type partition regions alternately arranged with each other. At least the n-type drift regions or p-type partition regions are formed by ion implantation under an acceleration voltage changed continuously. The p-type partition regions or n-type drift regions are formed by epitaxial growth or by diffusing impurities from the surface of a substrate or a layer for the layer.

Abstract: A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.

Abstract: This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.

Abstract: A MIS semiconductor device has a greatly improved relation between the on-resistance and the switching time by forming trench completely through a p base region and positioning the trench adjacent to a gate electrode, and then implanting n-type impurity ions using the gate electrode as a mask to form a second drain region, which also serves as a drift region.

Abstract: A semiconductor device is provided which can be manufactured even by using an inexpensive FZ wafer in a wafer process and still has a sharp inclination of a high impurity concentration in a high impurity concentration layer at the outermost portion of the reverse side and at the boundary between the high impurity concentration and a low impurity concentration drift layer, thus achieving both low cost and a high performance. A method for manufacturing a semiconductor device is also provided which can form a high impurity concentration buffer layer and a high impurity concentration layer at the outermost portion of the reverse side without any significant trouble, even after the formation of an active region and an electrode thereof at the right side, to thereby achieve both low cost and high performance.

Abstract: A semiconductor device is provided which can be manufactured even by using an inexpensive FZ wafer in a wafer process and still has a sharp inclination of a high impurity concentration in a high impurity concentration layer at the outermost portion of the reverse side and at the boundary between the high impurity concentration and a low impurity concentration drift layer, thus achieving both low cost and a high performance. A method for manufacturing a semiconductor device is also provided which can form a high impurity concentration buffer layer and a high impurity concentration layer at the outermost portion of the reverse side without any significant trouble, even after the formation of an active region and an electrode thereof at the right side, to thereby achieve both low cost and high performance.