Patents by Inventor Tatsuhiko Fujihira

Tatsuhiko Fujihira has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6462382
    Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: October 8, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kazuhiko Yoshida, Tatsuhiko Fujihira, Motoi Kudoh, Shoichi Furuhata, Shigeyuki Takeuchi
  • Publication number: 20020105025
    Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.
    Type: Application
    Filed: April 5, 2002
    Publication date: August 8, 2002
    Inventor: Tatsuhiko Fujihira
  • Publication number: 20020105024
    Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.
    Type: Application
    Filed: April 5, 2002
    Publication date: August 8, 2002
    Inventor: Tatsuhiko Fujihira
  • Publication number: 20020105027
    Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.
    Type: Application
    Filed: April 5, 2002
    Publication date: August 8, 2002
    Inventor: Tatsuhiko Fujihira
  • Publication number: 20020105028
    Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.
    Type: Application
    Filed: April 5, 2002
    Publication date: August 8, 2002
    Inventor: Tatsuhiko Fujihira
  • Publication number: 20020105026
    Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.
    Type: Application
    Filed: April 5, 2002
    Publication date: August 8, 2002
    Inventor: Tatsuhiko Fujihira
  • Publication number: 20020088990
    Abstract: A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.
    Type: Application
    Filed: October 17, 2001
    Publication date: July 11, 2002
    Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato
  • Publication number: 20020060330
    Abstract: A bidirectional semiconductor device facilitates making a current flow from the first MOSFET to the second MOSFET and vice versa across low on-resistance and exhibits a high breakdown voltage. The bidirectional semiconductor device includes a first n-channel MOSFET including base regions, a second n-channel MOSFET including base regions, and an alternating conductivity type layer formed of drift region and partition regions arranged alternately. Partition regions are isolated from base regions by a high resistivity region and from base regions by a high resistivity region to maintaining a high breakdown voltage between first MOSFET and the second MOSFET. By connecting high resistivity regions and via drift regions to each other, a current is made flow from the first MOSFET to the second MOSFET and vice versa and the on-voltage is reduced.
    Type: Application
    Filed: June 28, 2001
    Publication date: May 23, 2002
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
  • Patent number: 6383836
    Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least {fraction (1/100)} of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: May 7, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tatsuhiko Fujihira, Yasushi Miyasaka
  • Publication number: 20020027237
    Abstract: The super-junction semiconductor device facilitates increased switching speed and reduced on-resistance, and it includes an alternating conductivity type layer 11 formed of n-type drift regions 11a and p-type partition regions 11b arranged alternately, a pair of the n-type drift region 11a and p-type partition region 11b being repeated at a repeating pitch P1, and trenches 14, each containing a gate electrode 16 buried therein, the trenches 14 being arranged repeatedly at a repeating pitch P2 wider than the repeating pitch P1. The device further includes one or more n-type channel regions between a p-type partition regions 11b and a p-type well region 12.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 7, 2002
    Applicant: Fuji Electric Co., Ltd..
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato
  • Publication number: 20010052601
    Abstract: A semiconductor device facilitates preventing hot carriers from being injected into the insulation film so that the characteristics and the reliability of the active region thereof may not be impaired. The device includes an alternating-conductivity-type drain including heavily doped p-type breakdown voltage limiter regions in the portions of p-type partition regions in contact with the well bottoms of p-type base regions. Since the electric field in the central portion of breakdown voltage limiter regions reaches the critical value in advance to the electric field at the points E beneath gate insulation films the electric field at the points E is relaxed and hot carrier injection into gate insulation films is prevented.
    Type: Application
    Filed: May 1, 2001
    Publication date: December 20, 2001
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
  • Publication number: 20010050394
    Abstract: A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.
    Type: Application
    Filed: April 27, 2001
    Publication date: December 13, 2001
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Susumu Iwamoto, Takahiro Sato
  • Publication number: 20010046739
    Abstract: This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.
    Type: Application
    Filed: July 16, 2001
    Publication date: November 29, 2001
    Applicant: Fuji Electric, Co., Ltd.
    Inventors: Yasushi Miyasaka, Tatsuhiko Fujihira, Yasuhiko Ohnishi, Katsunori Ueno, Susumu Iwamoto
  • Patent number: 6323539
    Abstract: A high voltage integrated circuit is provided that includes a first region of first conductivity type; a second region of second conductivity type formed in a first major surface of the first region; a third region of first conductivity type formed in a selected area of a surface of the second region; first source region and first drain region of the first conductivity type formed in the second region, apart from the third region; a first gate electrode formed on a surface of the second region between the first source region and first drain region, through an insulating film; second source region and second drain region of second conductivity type formed in a surface of the third region; and a second gate electrode formed on a surface of the third region between the second source region and the second drain region, through an insulating film.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: November 27, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tatsuhiko Fujihira, Yukio Yano, Shigeyuki Obinata, Naoki Kumagai
  • Publication number: 20010042886
    Abstract: A depletion type MOS semiconductor device is provided which includes a p− well region formed in a surface layer of an n− drift layer, an n+ emitter region formed in a surface layer of the p− well region, an n− depletion region formed in the surface layer of the p− well region, to extend from the n+ emitter region to a surface layer of the n− drift layer, a gate electrode layer formed on a gate insulating film, over the n− depletion region, an emitter electrode formed in contact with surfaces of both of the n+ emitter region and the p− well region, and a collector electrode formed on a rear surface of the n− drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (gm) of the MOSFET or IGBT.
    Type: Application
    Filed: March 6, 2001
    Publication date: November 22, 2001
    Applicant: Fuji Electric, Co., Ltd.
    Inventors: Kazuhiko Yoshida, Motoi Kudoh, Tatsuhiko Fujihira
  • Publication number: 20010035560
    Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least {fraction (1/100)} of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.
    Type: Application
    Filed: February 26, 2001
    Publication date: November 1, 2001
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Tatsuhiko Fujihira, Yasushi Miyasaka
  • Publication number: 20010032998
    Abstract: A super-junction semiconductor is provided that facilitates easy mass-production thereof, reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the current capacity thereof. The super-junction semiconductor device includes a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer on low resistance layer, and a second alternating conductivity type layer on the first alternating conductivity type layer. The first alternating conductivity type layer including regions of a first conductivity type and regions of a second conductivity type arranged alternately with each other.
    Type: Application
    Filed: March 19, 2001
    Publication date: October 25, 2001
    Inventors: Susumu Iwamoto, Tatsuhiko Fujihira, Katsunori Ueno, Yasuhiko Onishi, Takahiro Sato
  • Publication number: 20010028083
    Abstract: Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted.
    Type: Application
    Filed: February 9, 2001
    Publication date: October 11, 2001
    Inventors: Yasuhiko Onishi, Tatsuhiko Fujihira, Katsunori Ueno, Susumu Iwamoto, Takahiro Sato, Tatsuji Nagaoka
  • Patent number: 6294818
    Abstract: A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurality of second conductive type compartment regions in which each of the compartment regions is positioned among the adjacent drift regions in parallel to make p-n junctions, respectively.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: September 25, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tatsuhiko Fujihira
  • Patent number: 6291856
    Abstract: This invention clarifies the effects of parameters and enables the mass production of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. The quantity of impurities in n drift regions is within the range between 100% and 150% or between 110% and 150% of the quantity of impurities in p partition regions. The impurity density of either one of the n drift regions and the p partition regions is within the range between 92% and 108% of the impurity density of the other regions. In addition, the width of either one of the n drift regions and the p partition regions is within the range between 94% and 106% of the width of the other regions.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: September 18, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Yasushi Miyasaka, Tatsuhiko Fujihira, Yasuhiko Ohnishi, Katsunori Ueno, Susumu Iwamoto