Abstract: Provided is an organic EL display device including a resin substrate layer, a TFT layer provided on the resin substrate layer, and a light-emitting element that is provided on the TFT layer and constitutes a display region. The resin substrate layer includes a first resin layer, an inorganic layer, and a second resin layer, which are provided in that order from a side opposite to the TFT layer. The interior of the first resin layer contains a plurality of air bubbles.

Abstract: Provided is a touch-panel-equipped display device that can achieve a desired touch detection performance even if it has a large-size high-definition panel. The touch-panel-equipped display device of the present invention includes an active matrix substrate (1). The active matrix substrate (1) includes, on a substrate (40), a plurality of pixel electrodes, a plurality of counter electrodes (21), and an insulating film (46) provided between the pixel electrodes and the counter electrodes (21). The active matrix substrate (1) further includes a plurality of signal lines (22) each of which is connected with any one of the counter electrodes (21), a plurality of switching elements that are connected with the pixel electrodes, respectively, and an organic insulating film (45) that is provided between the pixel electrodes and the signal lines (22) as well as the switching elements. The signal lines (22) are in contact with the substrate (40).

Abstract: Provided is a touch-panel-equipped display device that can achieve a desired touch detection performance even if it has a large-size high-definition panel. The touch-panel-equipped display device of the present invention includes an active matrix substrate (1). The active matrix substrate (1) includes, on a substrate (40), a plurality of pixel electrodes, a plurality of counter electrodes (21), and an insulating film (46) provided between the pixel electrodes and the counter electrodes (21). The active matrix substrate (1) further includes a plurality of signal lines (22) each of which is connected with any one of the counter electrodes (21), a plurality of switching elements that are connected with the pixel electrodes, respectively, and an organic insulating film (45) that is provided between the pixel electrodes and the signal lines (22) as well as the switching elements. The signal lines (22) are in contact with the substrate (40).

Abstract: Provided is an organic EL display device including a resin substrate layer, a TFT layer provided on the resin substrate layer, and a light-emitting element that is provided on the TFT layer and constitutes a display region. The resin substrate layer includes a first resin layer, an inorganic layer, and a second resin layer, which are provided in that order from a side opposite to the TFT layer. The interior of the first resin layer contains a plurality of air bubbles.

Abstract: A display device according to an aspect of the present invention includes a plurality of connection terminals and a plurality of lead lines, and the plurality of lead lines includes first lead lines, second lead lines, and third lead lines. Signal-line-side first lead lines are formed of a first conductive layer, signal-line-side second lead lines are formed of a second conductive layer, and signal-line-side third lead lines are formed of a third conductive layer. A lowest conductive layer of each switching element is formed of the second conductive layer. Among the plurality of lead lines, the connection-terminal-side first lead lines, the connection-terminal-side second lead lines, and the connection-terminal-side third lead lines are formed of conductive layers that include at least the third conductive layer but do not include the first conductive layer.

Abstract: A semiconductor device (100A) is provided with: a gate electrode (3); an oxide semiconductor layer (5); a thin-film transistor (101) including a gate insulating layer (4), a source electrode (7S), and a drain electrode (7D); an inter-layer insulating layer (11) arranged so as to cover the thin-film transistor (101) and come into contact with a channel area (5c) of the thin-film transistor (101); and a transparent electroconductive layer (19) arranged on the inter-layer insulating layer (11), the source electrode (7S) and the drain electrode (7D) each having a copper layer (7a), and the device being further provided with a copper oxide film (8) arranged between the source and drain electrodes and the inter-layer insulating layer (11). The inter-layer insulating layer (11) covers the drain electrode (7D) with the copper oxide film (8) interposed therebetween.

Abstract: A display device according to an aspect of the present invention includes a plurality of connection terminals and a plurality of lead lines, and the plurality of lead lines includes first lead lines, second lead lines, and third lead lines. Signal-line-side first lead lines are formed of a first conductive layer, signal-line-side second lead lines are formed of a second conductive layer, and signal-line-side third lead lines are formed of a third conductive layer. A lowest conductive layer of each switching element is formed of the second conductive layer. Among the plurality of lead lines, the connection-terminal-side first lead lines, the connection-terminal-side second lead lines, and the connection-terminal-side third lead lines are formed of conductive layers that include at least the third conductive layer but do not include the first conductive layer.

Abstract: A semiconductor device includes a substrate and a thin film transistor supported by the substrate. The thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and source and drain electrodes electrically connected to the oxide semiconductor layer. The gate insulating layer includes a first portion which is covered with the oxide semiconductor layer and a second portion which is adjacent to the first portion and which is not covered with any of the oxide semiconductor layer, the source electrode and the drain electrode. The second portion is smaller in thickness than the first portion, and the difference in thickness between the second portion and the first portion is more than 0 nm and not more than 50 nm.

Abstract: A display device according to an aspect of the present invention includes a first substrate, a second substrate, a liquid crystal layer, a plurality of signal lines, a plurality of switching elements, a plurality of connection terminals, and a plurality of lead lines. The plurality of lead lines include: first lead lines formed of a first conductive layer; second lead lines formed of a second conductive layer provided on a first insulating film covering the first lead lines; and third lead lines formed of a third conductive layer provided on a second insulating film covering the second lead lines. Among a plurality of conductive layers forming the switching elements, the lowest conductive layer is formed of the second conductive layer.

Abstract: A semiconductor device includes a thin-film transistor (101), a terminal portion (102), an interlevel insulating layer (14) including a first insulating layer (12) which contacts with the surface of a drain electrode (11d), and a first transparent conductive layer (15), a first dielectric layer (17) and a second transparent conductive layer (19a) formed on the interlevel insulating layer (14). The terminal portion (102) includes a lower conductive layer (3t), a second semiconductor layer (7t) arranged on a gate insulating layer (5), and lower and upper transparent connecting layers (15t, 19t). The gate insulating layer (5) and the second semiconductor layer (7t) have a contact hole (CH2), and their side surfaces located on a side of the contact hole (CH2) are aligned with each other. The lower transparent connecting layer (15t) contacts with the lower conductive layer (3t) in the contact hole (CH2).

Abstract: A semiconductor device (100) is provided with a thin film transistor including an oxide semiconductor layer (5), a gate electrode (3), a gate insulating layer (4), and a source electrode (7s) and a drain electrode (7d) that are in contact with the oxide semiconductor layer, at least one electrode of the source electrode (7s), the drain electrode (7d), and the gate electrode (3) has a multilayer structure that includes a first layer (3A, 7A) containing copper and a second layer (3B, 7B) containing titanium or molybdenum, the thickness of the first layer (3A, 7A) is more than the thickness of the second layer (3B, 7B), when the source electrode (7s) or the drain electrode (7d) has the multilayer structure, the second layer is arranged on the oxide semiconductor layer side of the first layer so as to be in contact with the surface of the oxide semiconductor layer (5), when the gate electrode (3) has the multilayer structure, the second layer is arranged on the substrate (1) side of the first layer, and the thick

Abstract: This semiconductor device (100) includes: a thin-film transistor (101); an interlevel insulating layer (14) including a first insulating layer (12); a first transparent conductive layer (15) formed on the interlevel insulating layer and having a first hole (15p); a dielectric layer (17) covering the side surface of the first transparent conductive layer closer to the first hole; and a second transparent conductive layer (19a) overlapping at least partially with the first transparent conductive layer via the dielectric layer, which has a second hole (17p). The first insulating layer has a third hole (12p). The interlevel insulating layer and dielectric layer have a first contact hole (CH1), the sidewall of which includes the side surfaces of the second and third holes (17p, 12p). At least a part of the side surface of the third hole is aligned with that of the second hole.

Abstract: An active matrix substrate includes a first TFT (10), a second TFT (20) disposed per pixel, and a circuit including the first TFT. The first and second TFTs each include a gate electrode (102A, 102B), a gate insulating layer (103), an oxide semiconductor layer (104A, 104B), and source and drain electrodes in contact with an upper surface of the oxide semiconductor layer. The oxide semiconductor layer (104A, 104B) has a stacked structure including a first semiconductor layer (104e, 104c) in contact with the source and drain electrodes and a second semiconductor layer that is disposed on a substrate-side of the first semiconductor layer and that has a smaller energy gap than the first semiconductor layer. The oxide semiconductor layers (104A) and (104B) are different from each other in terms of the composition and/or the number of stacked layers. The first TFT has a larger threshold voltage than the second TFT.

Abstract: A semiconductor device (100A) is provided with: a gate electrode (3); an oxide semiconductor layer (5); a thin-film transistor (101) including a gate insulating layer (4), a source electrode (7S), and a drain electrode (7D); an inter-layer insulating layer (11) arranged so as to cover the thin-film transistor (101) and come into contact with a channel area (5c) of the thin-film transistor (101); and a transparent electroconductive layer (19) arranged on the inter-layer insulating layer (11), the source electrode (7S) and the drain electrode (7D) each having a copper layer (7a), and the device being further provided with a copper oxide film (8) arranged between the source and drain electrodes and the inter-layer insulating layer (11). The inter-layer insulating layer (11) covers the drain electrode (7D) with the copper oxide film (8) interposed therebetween.

Abstract: A semiconductor film 21 is provided so as to overlap with a light-shielding film 11 when viewed in a plan view. A second insulating film 30 has a contact hole CH1 that reaches a source electrode 22 and a drain electrode 23. A gate electrode 41 is provided on the second insulating film 30 so as to overlap with the semiconductor film 21 when viewed in a plan view, and at the same time, so as to overlap with none of the source electrode 22 and the drain electrode 23 when viewed in a plan view. A third insulating film 50 is provided on the second insulating film 30 so as to cover the gate electrode 41, and at the same time, so as to be in contact with the source electrode 22 and the drain electrode 23 through the contact hole CH1.

Abstract: A display device according to an aspect of the present invention includes a first substrate, a second substrate, a liquid crystal layer, a plurality of signal lines, a plurality of switching elements, a plurality of connection terminals, and a plurality of lead lines. The plurality of lead lines include: first lead lines formed of a first conductive layer; second lead lines formed of a second conductive layer provided on a first insulating film covering the first lead lines; and third lead lines formed of a third conductive layer provided on a second insulating film covering the second lead lines. Among a plurality of conductive layers forming the switching elements, the lowest conductive layer is formed of the second conductive layer.

Abstract: A semiconductor device (100A) includes a substrate (101) and a thin film transistor (10) supported by the substrate. The thin film transistor includes a gate electrode (102), an oxide semiconductor layer (104), a gate insulating layer (103), a source electrode (105) and a drain electrode (106). The oxide semiconductor layer includes an upper semiconductor layer (104b) which is in contact with the source electrode and the drain electrode and which has a first energy gap, and a lower semiconductor layer (104a) which is provided under the upper semiconductor layer and which has a second energy gap that is smaller than the first energy gap. The source electrode and the drain electrode include a lower layer electrode (105a, 106a) which is in contact with the oxide semiconductor layer and which does not contain Cu, and a major layer electrode (105b, 106b) which is provided over the lower layer electrode and which contains Cu.

Abstract: A semiconductor device (100) includes: a substrate (10); and a thin film transistor (5) supported on the substrate, the thin film transistor including a gate electrode (12), an oxide semiconductor layer (18), a gate insulating layer (20) provided between the gate electrode and the oxide semiconductor layer, and a source electrode (14) and a drain electrode (16) electrically connected to the oxide semiconductor layer, wherein: the drain electrode is shaped so as to project toward the oxide semiconductor layer; a width W1 and a width W2 satisfy a relationship |W1?W2|?1 ?m, where the width W1 is a width of the oxide semiconductor layer in a channel width direction of the thin film transistor, and the width W2 is a width of the drain electrode in a direction perpendicular to a direction in which the drain electrode projects; and the width W1 and the width W2 are 3 ?m or more and 6 ?m or less.

Abstract: A semiconductor device (100A) includes: a substrate (1); a thin film transistor (101) whose active layer is an oxide semiconductor layer 5; at least one metal wiring layer including copper (7S, 7D); a metal oxide film including copper (8) arranged on an upper surface of the at least one metal wiring layer (7S, 7D); an insulating layer (11) covering at least one metal wiring layer with the metal oxide film (8) interposed therebetween; and a conductive layer (19) in direct contact with a portion of the at least one metal wiring layer, without the metal oxide film (8) interposed therebetween, in an opening formed in the insulating layer (11).

Abstract: A semiconductor device includes a thin-film transistor (101), a terminal portion (102), an interlevel insulating layer (14) including a first insulating layer (12) which contacts with the surface of a drain electrode (11d), and a first transparent conductive layer (15), a first dielectric layer (17) and a second transparent conductive layer (19a) formed on the interlevel insulating layer (14). The terminal portion (102) includes a lower conductive layer (3t), a second semiconductor layer (7t) arranged on a gate insulating layer (5), and lower and upper transparent connecting layers (15t, 19t). The gate insulating layer (5) and the second semiconductor layer (7t) have a contact hole (CH2), and their side surfaces located on a side of the contact hole (CH2) are aligned with each other. The lower transparent connecting layer (15t) contacts with the lower conductive layer (3t) in the contact hole (CH2).