Patents by Inventor Tetsuo Matsuda

Tetsuo Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040195106
    Abstract: The present invention relates to a plating method and a plating apparatus which can attain embedding of copper into fine interconnection patterns with use of a plating liquid having high throwing power and leveling properties, and which can make film thickness of a plated film substantially equal between an interconnection region and a non-interconnection region. A plating method comprises filling a plating liquid containing metal ions and an additive into a plating space formed between a substrate and an anode disposed closely to the substrate so as to face the substrate, and changing concentration of the additive in the plating liquid filled into the plating space during a plating process.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 7, 2004
    Inventors: Koji Mishima, Hiroaki Inoue, Natsuki Makino, Junji Kunisawa, Kenji Nakamura, Tetsuo Matsuda, Hisashi Kaneko, Toshiyuki Morita
  • Publication number: 20040174866
    Abstract: In a remote access server (RAS), the number of logical link resources, which are circuit resources between the RAS and an ISP server, is set greater than the number of physical link resources, which are circuit resources between the RAS and each terminal device. In the RAS, when a particular circuit undergoes a transition to the dormant state, only the physical link resource is released to allow use by other terminal devices while the logical link resource is maintained unchanged in a connected state, whereby the loss probability is reduced without increasing the number of physical link resources.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 9, 2004
    Applicant: NEC CORPORATION
    Inventors: Tetsuo Matsuda, Masayuki Yamada, Kazuhiko Azuma, Toshikazu Maruyama
  • Patent number: 6787827
    Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: September 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiji Inumiya, Katsuhiko Hieda, Tetsuo Matsuda, Yoshio Ozawa
  • Patent number: 6767437
    Abstract: In an electroplating apparatus, an electrolytic agent is filled into the portion between an anode and a dummy cathode which is opposite substantially face to face and parallel to the anode, and an electric current is supplied to this portion, thereby suppressing changes in properties of a black film during the period in which plating to a substrate to be processed is stopped. In particular, by applying an electric current to the anode immediately before plating to the substrate is resumed, the film formation characteristics of plating to the substrate can be maximally stabilized. This can reduce the consumption power and dissolution of the anode. This apparatus is particularly effective in copper plating in which the formation of a black film is significant.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: July 27, 2004
    Assignees: Kabushiki Kaisha Toshiba, Ebara Corporation
    Inventors: Tetsuo Matsuda, Hisashi Kaneko, Koji Mishima, Natsuki Makino, Junji Kunisawa
  • Patent number: 6764585
    Abstract: An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: July 20, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Hiroshi Toyoda, Hisashi Kaneko
  • Patent number: 6750143
    Abstract: A desired plating film is formed on a surface of a substrate to be treated by performing a film-depositing step based on electroless plating and an etching step alternately and repeatedly. In the film-depositing step, an electroless plating solution is supplied from a nozzle to the surface of the substrate. In the etching step, an etching solution is supplied from a nozzle to the surface of the substrate.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: June 15, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Iijima, Tetsuo Matsuda
  • Patent number: 6746589
    Abstract: The present invention relates to a plating method and a plating apparatus which can attain embedding of copper into fine interconnection patterns with use of a plating liquid having high throwing power and leveling properties, and which can make film thickness of a plated film substantially equal between an interconnection region and a non-interconnection region. A plating method comprises filling a plating liquid containing metal ions and an additive into a plating space formed between a substrate and an anode disposed closely to the substrate so as to face the substrate, and changing concentration of the additive in the plating liquid filled into the plating space during a plating process.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: June 8, 2004
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Koji Mishima, Hiroaki Inoue, Natsuki Makino, Junji Kunisawa, Kenji Nakamura, Tetsuo Matsuda, Hisashi Kaneko, Toshiyuki Morita
  • Publication number: 20040069646
    Abstract: A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.
    Type: Application
    Filed: August 1, 2003
    Publication date: April 15, 2004
    Inventors: Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Koji Mishima, Kenji Nakamura, Hiroaki Inoue, Norio Kimura, Tetsuo Matsuda, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura, Manabu Tsujimura, Toshiyuki Morita
  • Publication number: 20040050711
    Abstract: The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.
    Type: Application
    Filed: September 12, 2003
    Publication date: March 18, 2004
    Inventors: Koji Mishima, Mizuki Nagai, Ryoichi Kimizuka, Tetsuo Matsuda, Hisashi Kaneko
  • Publication number: 20040005774
    Abstract: A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (=removal rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.
    Type: Application
    Filed: June 23, 2003
    Publication date: January 8, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Hiroyuki Yano, Gaku Minamihaba, Dai Fukushima, Tetsuo Matsuda, Hisashi Kaneko
  • Publication number: 20030214010
    Abstract: A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.
    Type: Application
    Filed: April 29, 2003
    Publication date: November 20, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Tetsuo Matsuda, Hisashi Kaneko, Hideaki Hirabayashi
  • Patent number: 6638411
    Abstract: The present invention relates to a method and apparatus for separating out metal copper according to an electroplating of copper using, for example, a solution of copper sulfate to produce copper interconnections on a surface of a substrate. The substrate is brought into contact, at least once, with a processing solution containing at least one of organic substance and sulfur compound which are contained in a plating solution. Thereafter, the substrate is brought into contact with the plating solution to plate the substrate.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: October 28, 2003
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Koji Mishima, Mizuki Nagai, Ryoichi Kimizuka, Tetsuo Matsuda, Hisashi Kaneko
  • Patent number: 6632335
    Abstract: A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: October 14, 2003
    Assignees: Ebara Corporation, Kabushiki Kaisha Toshiba
    Inventors: Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Koji Mishima, Kenji Nakamura, Hiroaki Inoue, Norio Kimura, Tetsuo Matsuda, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura, Manabu Tsujimura, Toshiyuki Morita
  • Patent number: 6632476
    Abstract: After a thin liquid agent film is formed by supplying a liquid agent onto a plate-like developer holder, this liquid agent film and the surface of a substrate are opposed. The liquid agent film and the substrate are brought into contact with each other at a point by declining the substrate and moving it close to the liquid agent film, or by curving the substrate toward the liquid agent film. Then, the substrate is made parallel to the liquid agent film, and the liquid agent is supplied such that the contact area of the liquid agent film spreads over the entire surface by the interfacial tension between the liquid agent film and the substrate. Since a thin liquid agent film can be uniformly formed below the substrate, processing can be performed with a small consumption amount. Additionally, the liquid agent can be supplied to the substrate without holding air.
    Type: Grant
    Filed: March 14, 2001
    Date of Patent: October 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroko Nakamura, Hisashi Kaneko, Tetsuo Matsuda
  • Patent number: 6611060
    Abstract: A method of forming a cap film comprises a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film), and a second polishing step of performing a polishing operation at selectivity of R2 (=removal rate for the cap film/removal rate for the insulating film). Each of the polishing operations is performed by using a slurry having the condition of R1>R2. By performing the polishing operations at different selectivity, the cap film free from problems such as dishing of the cap film and the residual cap film on side walls of a recess is formed. Consequently, a semiconductor device having an excellent RC characteristic can be provided.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: August 26, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Hiroyuki Yano, Gaku Minamihaba, Dai Fukushima, Tetsuo Matsuda, Hisashi Kaneko
  • Patent number: 6579785
    Abstract: A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: June 17, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Toyoda, Tetsuo Matsuda, Hisashi Kaneko, Hideaki Hirabayashi
  • Patent number: 6563308
    Abstract: A thickness measuring system comprises: an eddy current loss measuring sensor having an exciting coil for receiving a high frequency current to excite a high frequency magnetic field to excite an eddy current in a conductive film, and a receiving coil for outputting the high frequency current which is influenced by an eddy current loss caused by the eddy current; an impedance analyzer for measuring the variation in impedance of the eddy current loss measuring sensor, the variation in current value of the high frequency current or the variation in phase of the high frequency current on the basis of the high frequency current outputted from the receiving coil; an optical displacement sensor for measuring the distance between the conductive film and the eddy current loss measuring sensor; and a control computer including a thickness calculating part for calculating the thickness of the conductive film on the basis of various measured results of the impedance analyzer and optical displacement sensor, and the eddy
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: May 13, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Nagano, Yuichiro Yamazaki, Motosuke Miyoshi, Hisashi Kaneko, Tetsuo Matsuda
  • Publication number: 20030067298
    Abstract: A thickness measuring system comprises: an eddy current loss measuring sensor having an exciting coil for receiving a high frequency current to excite a high frequency magnetic field to excite an eddy current in a conductive film, and a receiving coil for outputting the high frequency current which is influenced by an eddy current loss caused by the eddy current; an impedance analyzer for measuring the variation in impedance of the eddy current loss measuring sensor, the variation in current value of the high frequency current or the variation in phase of the high frequency current on the basis of the high frequency current outputted from the receiving coil; an optical displacement sensor for measuring the distance between the conductive film and the eddy current loss measuring sensor; and a control computer including a thickness calculating part for calculating the thickness of the conductive film on the basis of various measured results of the impedance analyzer and optical displacement sensor, and the eddy
    Type: Application
    Filed: March 27, 2001
    Publication date: April 10, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Osamu Nagano, Yuichiro Yamazaki, Motosuke Miyoshi, Hisashi Kaneko, Tetsuo Matsuda
  • Patent number: 6518177
    Abstract: A semiconductor device is formed by a compound film &agr;&ggr;x made of at least one element &agr; selected from metal elements and at least one element &ggr; selected from the group consisting of boron, carbon, and nitrogen on a base layer containing oxygen (O), and forming a compound film &agr;&ggr;yOz by causing the compound film &agr;&ggr;x to reduce the base layer and thereby oxidizing the compound film &agr;&ggr;x on an interface of the compound film &agr;&ggr;x and the base layer, wherein each of x and y is a ratio of the number of atoms of the element &ggr; to the number of atoms of the element &agr;, and z is a ratio of the number of atoms of the oxygen to the number of atoms of the element &agr;.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: February 11, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Kawanoue, Junichi Wada, Tetsuo Matsuda, Hisashi Kaneko
  • Publication number: 20030024431
    Abstract: The present invention provides an electroless plating liquid which allows a plating rate to be controlled, is not largely influential on semiconductor characteristics, and poses no problem on the health of workers, and a method of forming an interconnection according to a electroless plating process which uses such an electroless plating liquid. The electroless copper plating liquid contains dihydric copper ions, a complexing agent, an aldehyde acid, and an organic alkali. The electroless copper plating liquid is preferably be used in a method having the steps of forming an auxiliary seed layer for reinforcing a copper seed layer in an interconnection groove defined in a surface of a semiconductor device, and performing an electrolytic plating process using the seed layer including the auxiliary seed layer as a current feeding layer, for thereby filling copper in the interconnection groove defined in the surface of the semiconductor device.
    Type: Application
    Filed: March 12, 2002
    Publication date: February 6, 2003
    Inventors: Hiroaki Inoue, Koji Mishima, Kenji Nakamura, Shuichi Okuyama, Tetsuo Matsuda, Hisashi Kaneko