Patents by Inventor Tetsuo Matsuda
Tetsuo Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020117698Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.Type: ApplicationFiled: April 26, 2002Publication date: August 29, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Seiji Inumiya, Katsuhiko Hieda, Tetsuo Matsuda, Yoshio Ozawa
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Publication number: 20020096435Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.Type: ApplicationFiled: March 28, 2002Publication date: July 25, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Tetsuo Matsuda, Hisashi Kaneko, Katsuya Okumura
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Patent number: 6403997Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.Type: GrantFiled: July 21, 2000Date of Patent: June 11, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Seiji Inumiya, Katsuhiko Hieda, Tetsuo Matsuda, Yoshio Ozawa
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Patent number: 6403481Abstract: A film formation method for manufacture of a semiconductor device includes the steps of forming a first metal film as a continuous film on a substrate, forming a second metal film as discontinuous films on the substrate formed with the first metal film, and forming a third metal film by plating on the substrate formed with the first and second metal films.Type: GrantFiled: August 10, 1999Date of Patent: June 11, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuo Matsuda, Hisashi Kaneko
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Publication number: 20020056647Abstract: The present invention relates to a plating method and a plating apparatus which can attain embedding of copper into fine interconnection patterns with the use of a plating liquid having high throwing power and leveling properties, and which can make the film thickness of the plated film substantially equal between the interconnection region and the non-interconnection region, thereby facilitating a later CMP processing. A plating method comprising filling a plating liquid containing metal ions and an additive into a plating space formed between a substrate and an anode disposed closely to the substrate so as to face the substrate, and changing the concentration of the additive in the plating liquid filled into the plating space during a plating process.Type: ApplicationFiled: September 19, 2001Publication date: May 16, 2002Inventors: Koji Mishima, Hiroaki Inoue, Natsuki Makino, Junji Kunisawa, Kenji Nakamura, Tetsuo Matsuda, Hisashi Kaneko, Toshiyuki Morita
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Publication number: 20020050459Abstract: An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.Type: ApplicationFiled: November 1, 2001Publication date: May 2, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Tetsuo Matsuda, Hiroshi Toyoda, Hisashi Kaneko
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Patent number: 6375823Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.Type: GrantFiled: February 9, 2000Date of Patent: April 23, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuo Matsuda, Hisashi Kaneko, Katsuya Okumura
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Patent number: 6368951Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.Type: GrantFiled: July 13, 2001Date of Patent: April 9, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tetsuo Matsuda, Tadashi Iijima, Hisashi Kaneko, Hideki Shibata, Naofumi Nakamura, Minakshisundaran Balasubramanian Anand, Tadashi Matsuno, Katsuya Okumura
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Publication number: 20020033339Abstract: A substrate is plated with a metal film of uniform thickness only in a limited area thereof which is to be plated. A substrate plating apparatus has a substrate holder for holding a substrate and a plating cell for plating a portion of a surface, to be plated, of the substrate held by the substrate holder. The plating cell has an anode disposed so as to cover the portion of the surface, to be plated, of the substrate held by the substrate holder, a cathode for supplying a current to the surface, to be plated, of the substrate in such a state that the cathode is brought into contact with the substrate, a plating liquid supplying device for supplying a plating liquid between the anode and the surface, to be plated, of the substrate, and a power source for applying a voltage between the anode and the cathode.Type: ApplicationFiled: September 19, 2001Publication date: March 21, 2002Inventors: Norio Kimura, Koji Mishima, Junji Kunisawa, Hiroaki Inoue, Natsuki Makino, Tetsuo Matsuda, Hisashi Kaneko
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Publication number: 20020020627Abstract: This invention relates, particularly, to a plating method and apparatus for a substrate for uses, such as the filling of a metal, e.g., copper (Cu), into a fine interconnection pattern (recesses) formed in a semiconductor substrate.Type: ApplicationFiled: December 22, 2000Publication date: February 21, 2002Inventors: Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Koji Mishima, Kenji Nakamura, Hiroaki Inoue, Norio Kimura, Tetsuo Matsuda, Hisashi Kaneko, Nobuo Hayasaka, Katsuya Okumura, Manabu Tsujimura, Toshiyuki Morita
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Patent number: 6348402Abstract: A groove or hole is formed in an insulating layer formed on a semiconductor substrate, and a first conductive layer including a first metal element is formed on a surface of the insulating layer. By oxidizing the first conductive layer, an oxide layer of the first metal element is formed on a surface of the first conductive layer. A second conductive layer including a second metal element having a free energy of oxide formation lower than that of the first metal element is deposited thereon. By reducing the oxide layer of the first metal element by the second metal element, an oxide layer of the second metal element is formed at the interface between the first conductive layer and the second conductive layer. Further, an interconnection is buried in the groove or hole of the insulating layer.Type: GrantFiled: March 16, 2000Date of Patent: February 19, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Kawanoue, Tetsuo Matsuda, Hisashi Kaneko, Tadashi Iijima
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Patent number: 6342444Abstract: A TiN film is selectively formed as a barrier layer on a Cu metal layer by selective removal of a Ti metal layer on the Si metal layer after the following steps of selectively forming a Si metal layer as an etching mask on an insulation film, forming a trench pattern by selective removal of the insulation film using the Si metal layer, forming a Cu metal layer in the trench pattern with the Si metal layer remained, forming the Ti metal layer on the Si metal layer and the Cu metal layer as a barrier material with a different kind of eutectic reaction with Cu from the reaction with the etching mask by heat-treatment in an atmosphere of nitrogen, and selectively nitriding the Ti metal layer on the Cu metal layer by heat-treatment of the Ti metal layer in an atmosphere of nitrogen.Type: GrantFiled: March 10, 2000Date of Patent: January 29, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Higashi, Noriaki Matsunaga, Hiroshi Toyoda, Akihiro Kajita, Tetsuo Matsuda, Hisashi Kaneko
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Publication number: 20020000379Abstract: In an electroplating apparatus, an electrolytic agent is filled into the portion between an anode and a dummy cathode which is opposite substantially face to face and parallel to the anode, and an electric current is supplied to this portion, thereby suppressing changes in properties of a black film during the period in which plating to a substrate to be processed is stopped. In particular, by applying an electric current to the anode immediately before plating to the substrate is resumed, the film formation characteristics of plating to the substrate can be maximally stabilized. This can reduce the consumption power and dissolution of the anode. This apparatus is particularly effective in copper plating in which the formation of a black film is significant.Type: ApplicationFiled: May 21, 2001Publication date: January 3, 2002Inventors: Tetsuo Matsuda, Hisashi Kaneko, Koji Mishima, Natsuki Makino, Junji Kunisawa
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Patent number: 6333215Abstract: A method of manufacturing a semiconductor device, which comprises the steps of subjecting a solid material to a first treatment consisting of a thermal treatment and/or a chemical treatment thereby to obtain a treated solid material having desired properties, and adhering the treated solid material onto a substrate for the semiconductor device, thereby to form a thin film on the substrate.Type: GrantFiled: June 17, 1998Date of Patent: December 25, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuo Matsuda, Nobuo Hayasaka
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Publication number: 20010038147Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.Type: ApplicationFiled: July 13, 2001Publication date: November 8, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tetsuo Matsuda, Tadashi Iijima, Hisashi Kaneko, Hideki Shibata, Naofumi Nakamura, Minakshisundaran Balasubramanian Anand, Tadashi Matsuno, Katsuya Okumura
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Publication number: 20010033894Abstract: After a thin liquid agent film is formed by supplying a liquid agent onto a plate-like developer holder, this liquid agent film and the surface of a substrate are opposed. The liquid agent film and the substrate are brought into contact with each other at a point by declining the substrate and moving it close to the liquid agent film, or by curving the substrate toward the liquid agent film. Then, the substrate is made parallel to the liquid agent film, and the liquid agent is supplied such that the contact area of the liquid agent film spreads over the entire surface by the interfacial tension between the liquid agent film and the substrate. Since a thin liquid agent film can be uniformly formed below the substrate, processing can be performed with a small consumption amount. Additionally, the liquid agent can be supplied to the substrate without holding air.Type: ApplicationFiled: March 14, 2001Publication date: October 25, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroko Nakamura, Hisashi Kaneko, Tetsuo Matsuda
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Publication number: 20010024691Abstract: This invention relates to a semiconductor substrate processing apparatus and method for forming interconnects by filling a circuit pattern groove and/or a hole formed in a semiconductor substrate with a plated metal film, and removing the plated metal film while leaving the metal film at the filled portion. The apparatus comprises a carry-in and carry-out section for carrying in and carrying out a semiconductor substrate, which has a circuit formed on a surface thereof, in a dry state; a plated metal film forming unit for forming a plated metal film on the semiconductor substrate which has been carried in; a bevel etching unit for etching a peripheral edge portion of the semiconductor substrate; a polishing unit for polishing at least part of the plated metal film on the semiconductor substrate; and a transport mechanism for transporting the semiconductor substrate between the above units.Type: ApplicationFiled: May 25, 2001Publication date: September 27, 2001Inventors: Norio Kimura, Koji Mishima, Junji Kunisawa, Mitsuko Odagaki, Natsuki Makino, Manabu Tsujimura, Hiroaki Inoue, Kenji Nakamura, Moriji Matsumoto, Tetsuo Matsuda, Hisashi Kaneko, Toshiyuki Morita, Nobuo Hayasaka, Katsuya Okumura
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Patent number: 6291891Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.Type: GrantFiled: January 12, 1999Date of Patent: September 18, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tetsuo Matsuda, Tadashi Iijima, Hisashi Kaneko, Hideki Shibata, Naofumi Nakamura, Minakshisundaran Balasubramanian Anand, Tadashi Matsuno, Katsuya Okumura
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Publication number: 20010013617Abstract: A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.Type: ApplicationFiled: January 24, 2001Publication date: August 16, 2001Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi Toyoda, Tetsuo Matsuda, Hisashi Kaneko, Hideaki Hirabayashi
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Patent number: 6251763Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a position of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.Type: GrantFiled: June 29, 1998Date of Patent: June 26, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Seiji Inumiya, Katsuhiko Hieda, Tetsuo Matsuda, Yoshio Ozawa