Patents by Inventor Tetsuya Kawashima
Tetsuya Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100270989Abstract: A switching power supply that can suppress output variation at a time of transition of a control mode from a non-linear control mode to a linear control mode. The switching power supply includes instruction value forming circuitry that forms, in a linear control mode, a linear control instruction value for linearly control a switching circuit based on an error of an output voltage, and forms, in a non-linear control mode, a non-linear control instruction value for non-linearly control the switching circuit. The instruction value forming circuitry predicts, in the non-linear control mode, a linear control instruction value suited to the load current in the non-linear control mode, and uses the predicted linear control instruction value for an initial value of the linear control instruction value at a time of transition from the non-linear control mode to the linear control mode.Type: ApplicationFiled: April 28, 2010Publication date: October 28, 2010Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.Inventors: Masahiro Sasaki, Tetsuya Kawashima
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Publication number: 20100270992Abstract: A semiconductor device having two semiconductor chips sealed in a sealant (2-in-1 package) is provided. A power MOSFET chip for control is disposed on an input-side plate lead portion, wherein a source electrode and a gate electrode are formed on a main surface of the chip and the source electrode is connected to an output plate lead portion. A power MOSFET chip for synchronization is disposed on an output-side plate lead portion, wherein a source electrode and a gate electrode are formed on a main surface of the chip, and the second source electrode is connected to a ground-side plate lead portion. The ground-side plate lead portion and gate-side lead portions connected to the gate electrodes, respectively, are provided between the input-side plate lead portion and the output-side plate lead portion. In this manner, heat-dissipation paths via wirings when the 2-in-1 package is mounted on a board can be wide.Type: ApplicationFiled: April 26, 2010Publication date: October 28, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuya KAWASHIMA, Takayuki HASHIMOTO
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Patent number: 7812578Abstract: A DC-DC converter includes a series circuit of a main switch and a choke coil and an output capacitor connected to one end of the series circuit and outputs a DC voltage from the one end of the series circuit. A first MOS transistor is connected in parallel to the series circuit and a second MOS transistor is connected in parallel to the output capacitor. A control circuit controls the gate voltages of the first MOS transistor and/or the second MOS transistor so that the first MOS transistor and/or the second MOS transistor outputs a changed target output voltage, whereby the output voltage is made equal to the target voltage at high speed.Type: GrantFiled: June 3, 2008Date of Patent: October 12, 2010Assignee: Fuji Electric Systems Co., Ltd.Inventors: Satoshi Sugahara, Kouhei Yamada, Tetsuya Kawashima, Akira Yamazaki
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Patent number: 7782025Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.Type: GrantFiled: January 6, 2009Date of Patent: August 24, 2010Assignee: Renesas Electronics Corp.Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
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Publication number: 20100176430Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit.Type: ApplicationFiled: March 10, 2010Publication date: July 15, 2010Applicant: Renesas Technology Corp.Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
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Publication number: 20100127683Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: ApplicationFiled: January 28, 2010Publication date: May 27, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida
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Patent number: 7687885Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.Type: GrantFiled: May 30, 2007Date of Patent: March 30, 2010Assignee: Renesas Technology Corp.Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
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Patent number: 7679173Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: GrantFiled: January 24, 2007Date of Patent: March 16, 2010Assignee: Renesas Technology Corp.Inventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida
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Publication number: 20090154209Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.Type: ApplicationFiled: January 6, 2009Publication date: June 18, 2009Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
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Publication number: 20090096436Abstract: A DC-DC converter includes a series circuit of a main switch and a choke coil and an output capacitor connected to one end of the series circuit and outputs a DC voltage from the one end of the series circuit. A first MOS transistor is connected in parallel to the series circuit and a second MOS transistor is connected in parallel to the output capacitor. A control circuit controls the gate voltages of the first MOS transistor and/or the second MOS transistor so that the first MOS transistor and/or the second MOS transistor outputs a changed target output voltage, whereby the output voltage is made equal to the target voltage at high speed.Type: ApplicationFiled: June 3, 2008Publication date: April 16, 2009Applicant: Fuji Electric Device Technology Co., LtdInventors: Satoshi SUGAHARA, Kouhei Yamada, Tetsuya Kawashima, Akira Yamazaki
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Patent number: 7480163Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.Type: GrantFiled: October 24, 2006Date of Patent: January 20, 2009Assignee: Renesas Technology Corp.Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
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Publication number: 20070278516Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.Type: ApplicationFiled: May 30, 2007Publication date: December 6, 2007Applicant: Renesas Technology Corp.Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
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Publication number: 20070228534Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.Type: ApplicationFiled: January 24, 2007Publication date: October 4, 2007Inventors: Tomoaki Uno, Nobuyoshi Matsuura, Yukihiro Sato, Keiichi Okawa, Tetsuya Kawashima, Kisho Ashida
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Publication number: 20070200537Abstract: A power supply capable of reducing loss of large current and high frequency. In an MCM for power supply in which a high-side power MOSFET chip, a low-side power MOSFET chip and a driver IC chip driving them are sealed in one sealing material (a capsulating insulation resin), a wiring length of a wiring DL connecting an output terminal of the driver IC chip to a gate terminal of the low-side power MOSFET chip or a source terminal is made shorter than a wiring length of a wiring DH connecting the output terminal of the driver IC chip to a gate terminal of the high-side power MOSFET chip or a source terminal. Further, the number of the wiring DL is made larger than the number of the wiring DH.Type: ApplicationFiled: January 19, 2007Publication date: August 30, 2007Inventors: Noboru Akiyama, Takayuki Hashimoto, Masaki Shiraishi, Tetsuya Kawashima, Koji Tateno, Nobuyoshi Matsuura
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Publication number: 20070090814Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.Type: ApplicationFiled: October 24, 2006Publication date: April 26, 2007Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
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Patent number: 7145224Abstract: In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the source terminal ST1 is connected to the plate-like lead for source 12. Furthermore, a synchronous power MOSFET chip 3 is disposed on the output-side plate-like lead 6, and the drain terminal DT2 is formed on the rear surface of the chip 3 and the output-side plate-like lead 6 is connected to the drain terminal DT2. Furthermore, source terminal ST2 and gate terminal GT2 are formed on the principal surface of the synchronous power MOSFET chip 3, and the source terminal ST2 is connected to the plate-like lead for source 13. The plate-like leads for source 12 and 13 are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM 1.Type: GrantFiled: January 25, 2005Date of Patent: December 5, 2006Assignee: Renesas Technology Corp.Inventors: Tetsuya Kawashima, Akira Mishima
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Publication number: 20050161785Abstract: In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the source terminal ST1 is connected to the plate-like lead for source 12. Furthermore, a synchronous power MOSFET chip 3 is disposed on the output-side plate-like lead 6, and the drain terminal DT2 is formed on the rear surface of the chip 3 and the output-side plate-like lead 6 is connected to the drain terminal DT2. Furthermore, source terminal ST2 and gate terminal GT2 are formed on the principal surface of the synchronous power MOSFET chip 3, and the source terminal ST2 is connected to the plate-like lead for source 13. The plate-like leads for source 12 and 13 are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM 1.Type: ApplicationFiled: January 25, 2005Publication date: July 28, 2005Inventors: Tetsuya Kawashima, Akira Mishima
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Patent number: RE41869Abstract: In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the source terminal ST1 is connected to the plate-like lead for source 12. Furthermore, a synchronous power MOSFET chip 3 is disposed on the output-side plate-like lead 6, and the drain terminal DT2 is formed on the rear surface of the chip 3 and the output-side plate-like lead 6 is connected to the drain terminal DT2. Furthermore, source terminal ST2 and gate terminal GT2 are formed on the principal surface of the synchronous power MOSFET chip 3, and the source terminal ST2 is connected to the plate-like lead for source 13. The plate-like leads for source 12 and 13 are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM 1.Type: GrantFiled: May 30, 2008Date of Patent: October 26, 2010Assignee: Renesas Electronics Corp.Inventors: Tetsuya Kawashima, Akira Mishima