Abstract: The disclosed subject matter relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to photonic devices having thermally conductive layers for the removal of heat from optoelectronic components in the photonic devices.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes an optical component having a waveguide core, and multiple features positioned adjacent to the waveguide core. The waveguide core contains a first material having a first thermal conductivity, and the features contain a second material having a second thermal conductivity that is greater than the first thermal conductivity.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes an optical component having a waveguide core, and multiple features positioned adjacent to the waveguide core. The waveguide core contains a first material having a first thermal conductivity, and the features contain a second material having a second thermal conductivity that is greater than the first thermal conductivity.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes a substrate, an optical component including a waveguide core, and a back-end-of-line stack including a heat spreader layer. The optical component is positioned in a vertical direction between the substrate and the back-end-of-line stack. The waveguide core contains a first material having a first thermal conductivity, and the heat spreader layer contains a second material having a second thermal conductivity that is greater than the first thermal conductivity of the first material.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes a waveguide core and a back-end-of-line stack including a first metallization level, a second metallization level, and a heat sink having a metal feature in the second metallization level. The heat sink is positioned adjacent to a section of the waveguide core. The first metallization level including a dielectric layer positioned between the metal feature and the section of the waveguide core.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes a substrate, an optical component including a waveguide core, and a back-end-of-line stack including a heat spreader layer. The optical component is positioned in a vertical direction between the substrate and the back-end-of-line stack. The waveguide core contains a first material having a first thermal conductivity, and the heat spreader layer contains a second material having a second thermal conductivity that is greater than the first thermal conductivity of the first material.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes an optical component having a waveguide core, and multiple features positioned adjacent to the waveguide core. The waveguide core contains a first material having a first thermal conductivity, and the features contain a second material having a second thermal conductivity that is greater than the first thermal conductivity.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes a waveguide core and a back-end-of-line stack including a first metallization level, a second metallization level, and a heat sink having a metal feature in the second metallization level. The heat sink is positioned adjacent to a section of the waveguide core. The first metallization level including a dielectric layer positioned between the metal feature and the section of the waveguide core.

Abstract: The disclosed subject matter relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to photonic devices having thermally conductive layers for the removal of heat from optoelectronic components in the photonic devices.

Abstract: Structures for an edge coupler and methods of fabricating a structure for an edge coupler. A first waveguide core has a first section that has a tapered shape and a second section that is adjoined to the first section. Multiple segments are positioned with a spaced arrangement adjacent to an end surface of the second section of the first waveguide core. A slab layer is adjoined to the first section of the first waveguide core. A second waveguide core has a section that overlaps with the first section of the first waveguide core to define a layer stack. The section of the second waveguide core has a tapered shape, and the first and second waveguide cores are comprised of different materials. The first section of the first waveguide core has a first thickness, and the slab layer has a second thickness that is less than the first thickness.

Abstract: Structures that include a Bragg grating and methods of fabricating a structure that includes a Bragg grating. Bragg elements are positioned adjacent to a waveguide. The Bragg elements are separated by grooves that alternate with the Bragg elements. A dielectric layer includes portions positioned to close the grooves to define airgaps. The airgaps are respectively arranged between adjacent pairs of the Bragg elements. The Bragg elements may be used to form the Bragg grating.

Abstract: A vertically oriented self terminating semiconductor device such as a discrete trench MOS device (10, 38) that includes a cylindrical drift region (18) that extend downward from a surface region to a substrate (11) and a dielectric region (20) that exponentially tapers outward from the cylindrical drift region as the drift region approaches the substrate. A field plate electrode (12) is disposed on the dielectric region. Alternatively, the gate electrode (40, 46) may be disposed on the dielectric region, optionally with an underlying field plate electrode (48).

Abstract: The present invention provides a vertical tapered dielectric high-voltage device (10) in which the device drift region is depicted by action of MOS field plates (30) formed in vertical trenches. The high-voltage device comprises: a substrate (32); a silicon mesa (20) formed on the substrate and having a stripe geometry, wherein the silicon mesa provides a drift region having a constant doping profile; a recessed gate (22) and source (SN) formed on the silicon mesa; a trench (26) adjacent each side of the silicon mesa; and a metal-dielectric field plate structure (12) formed in each trench; wherein each metal-dielectric field plate structure comprises a dielectric (28) and a metal field plate (30) formed over the dielectric, and wherein a thickness of the dielectric increases linearly through a depth of the trench to provide a constant longitudinal electric field.

Abstract: A Silicon on Insulator device is disclosed wherein a parasitic channel induced in a thin film portion of the device is prevented from allowing current flow between the source and drain by a Deep N implant directly below the source or drain. The deep N implant prevents a depletion region from being formed, thereby cutting off current flow between the source and the drain that would otherwise occur.

Abstract: A field effect device includes at least one segmented field plate, each of the at least one segmented field plates having a plurality of segments that each form a plate of a capacitor, wherein the field effect device is connected to an electronic element that dynamically connects selected segments to selectively set a gate-to-drain and a drain-to-source capacitance. An ultrasonic device includes a transducer coupled to a switching device that switches the transducer between a transmit mode and a receive mode switching device, wherein the switching device includes the field effect device.

Abstract: An asymmetric semiconductor device (10) and method of forming the same in which 25V devices can be fabricated in processes with gate oxide thicknesses designed for 2.75 or 5.5V maximum operation. The device includes: a shallow trench isolation (STI) region (12) that forms a dielectric between a drain region (18) and a gate region (20) of a unit cell to allow for high voltage operation; and an n-type well (14) and a p-type well (24) patterned within the unit cell.

Abstract: A vertically oriented self terminating discrete trench MOS device (1) that includes a cylindrical drift region (18) that extend downward from a surface region to a substrate (11) and a dielectric region (20) that exponentially tapers outward from the cylindrical drift region as the drift region approaches the substrate.

Abstract: A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping (303) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a size and shape to permit the source (309) to be biased at a voltage significantly less than the handler wafer (304) and drain, a condition under which prior art SOI devices may not properly operate.

Abstract: The present invention provides a vertical tapered dielectric high-voltage device (10) in which the device drift region is depicted by action of MOS field plates (30) formed in vertical trenches. The high-voltage device comprises: a substrate (32); a silicon mesa (20) formed on the substrate and having a stripe geometry, wherein the silicon mesa provides a drift region having a constant doping profile; a recessed gate (22) and source (SN) formed on the silicon mesa; a trench (26) adjacent each side of the silicon mesa; and a metal-dielectric field plate structure (12) formed in each trench; wherein each metal-dielectric field plate structure comprises a dielectric (28) and a metal field plate (30) formed over the dielectric, and wherein a thickness of the dielectric increases linearly through a depth of the trench to provide a constant longitudinal electric field.

Abstract: In a lateral thin-film Silicon-On-Insulator (SOI) device, a field plate is provided to extend substantially over a lateral drift region to protect the device from package and surface charge effects. In particular, the field plate comprises a layer of plural metallic regions which are isolated laterally from one another by spacing so as to assume a lateral electric field profile which is established by a volume doping gradient in the silicon drift region.