Abstract: A field effect device includes at least one segmented field plate, each of the at least one segmented field plates having a plurality of segments that each form a plate of a capacitor, wherein the field effect device is connected to an electronic element that dynamically connects selected segments to selectively set a gate-to-drain and a drain-to-source capacitance. An ultrasonic device includes a transducer coupled to a switching device that switches the transducer between a transmit mode and a receive mode switching device, wherein the switching device includes the field effect device.

Abstract: A silicon-on-insulator (SOI) photodiode optical monitoring method and system for color temperature control in solid state light systems. The method includes the steps of providing a plurality of SOI photodiodes, wherein each SOI photodiode includes a silicon substrate, a buried oxide layer formed on the silicon substrate, and a silicon layer formed on the buried oxide layer, and wherein the silicon layer of each SOI photodiode has a different thickness, determining a proportion of incident light passing through each SOI photodiode to the silicon substrate with respect to wavelength and the thickness of the silicon layer, and calculating color component intensities of the incident light based on the determined proportions.

Abstract: An improved MOS device is disclosed that utilizes a voltage configuration shorting the body and the gate, and independently biasing the source. As a result, the device functions as a trench MOS device with an NPN bipolar transistor in parallel therewith, permitting a smaller size device to perform the DC-DC conversion only previously possible with conventional unipolar devices.

Abstract: A Silicon on Insulator (SOI) device is disclosed wherein an extension of P-type doping (303) is implanted between the buried oxide layer of the device and the SOI layer. The extension is of a size and shape to permit the source (309) to be biased at a voltage significantly less than the handler wafer (304) and drain, a condition under which prior art SOI devices may not properly operate.

Abstract: A Silicon on Insulator device is disclosed wherein a parasitic channel (110) induced in a thin film portion of the device is prevented from allowing current flow between the source (101) and drain (101) by a Deep N implant directly below the source or drain. The deep N implant prevents a depletion region from being formed, thereby cutting off current flow between the source (101) and the drain (101) that would otherwise occur.

Abstract: A dual gate oxide high-voltage semiconductor device and method for forming the same are provided. Specifically, a device formed according to the present invention includes a semiconductor substrate, a buried oxide layer formed over the substrate, a silicon layer formed over the buried oxide layer, and a top oxide layer formed over the silicon layer. Adjacent an edge of the top oxide layer, a dual gate oxide is formed. The dual gate oxide allows both specific-on-resistance and breakdown voltage of the device to be optimized.

Abstract: The present invention provides a semiconductor device of the SOI-LDMOS type in which the field plate is divided into a plurality of electrically isolated sub-field plates. At least two of the divided sub-field plates are connected to external circuits for reading their respective output voltages. By connecting a first external circuit and a second external circuit having specific components, one is configured for determining an instantaneous output voltage and the other is configured for determining a change in output voltage as a function of time. Power is disconnected from the semiconductor device if either the instantaneous voltage or the derivative of voltage over time exceeds an established value.

Abstract: The present invention provides a semiconductor device of the SOI-LDMOS type in which the field plate is divided into a plurality of electrically isolated sub-field plates. At least two of the divided sub-field plates are connected to external circuits for reading their respective output voltages. By connecting a first external circuit and a second external circuit having specific components, one is configured for determining an instantaneous output voltage and the other is configured for determining a change in output voltage as a function of time. Power is disconnected from the semiconductor device if either the instantaneous voltage or the derivative of voltage over time exceeds an established value.

Abstract: The present invention provides a semiconductor device of the SOI-LDMOS type in which the field plate is divided into a plurality of electrically isolated sub-field plates. At least two of the divided sub-field plates are connected to external circuits for reading their respective output voltages. By connecting a first external circuit and a second external circuit having specific components, one is configured for determining an instantaneous output voltage and the other is configured for determining a change in output voltage as a function of time. Power is disconnected from the semiconductor device if either the instantaneous voltage or the derivative of voltage over time exceeds an established value.

Abstract: A lateral insulated gate bipolar PMOS device includes a semiconductor substrate, a buried insulating layer and a lateral PMOS transistor device in an SOI layer on the buried insulating layer having a source region of p-type conductivity. A lateral drift region of n-type conductivity is provided adjacent the body region, and a drain region of the p-type conductivity is provided laterally spaced from the body region by the drift region. An n-type conductivity drain region is formed of a shallow n-type contact surface region inserted into a p-inversion buffer. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.

Abstract: A high-voltage capacitive voltage divider circuit includes a high-voltage Silicon-On-Insulator (SOI) capacitor connected between a high-voltage terminal and a low-voltage terminal, and a low-voltage SOI capacitor connected between the low-voltage terminal and a common terminal. The voltage divider circuit also includes control circuitry for processing a signal generated at the low-voltage terminal in order to provide voltage-related control of a larger circuit employing the voltage divider circuit. The high-voltage SOI capacitor can include an oxide layer on a substrate, with a thinned drift region on the oxide layer, a thick oxide layer over the thinned drift region, and an electrode layer over the thick oxide layer, with the electrode layer and the thinned drift region forming capacitor plates insulated from each other by the thick oxide layer.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by an insulation region.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral transistor device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region and forms a lightly-doped drain region, and a drain contact region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being at least substantially insulated from the body region and drift region by a surface insulation region.

Abstract: The present invention is directed to an SOI LDMOS device having improved current handling capability, particularly in the source-follower mode, while maintaining an improved breakdown voltage capability. The improvement in current handling capability is achieved in a first embodiment by introducing an offset region between the source and thin drift regions. The offset region achieves an offset between the onset of the linear doping profile and the thinning of the SOI layer that results in the thin drift region. In a second embodiment a further increase in the current handling capability of an SOI device is achieved by fabricating an oxide layer over the offset region, with the thickness of the oxide layer layer varying up to about half the thickness of the oxide layer fabricated over the thin drift region.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral MOS device on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first. A lateral drift region of a first conductivity type is provided adjacent the body region, and a drain region of the first conductivity type is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and over at least a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.

Abstract: A method of making a semiconductor device such as a diode or MOSFET provided in a thin semiconductor film on a thin buried oxide is disclosed, in which the lateral semiconductor device structure includes at least two semiconductor regions separated by a lateral drift region. A top oxide insulating layer is provided over the thin semiconductor film and a conductive field plate is provided on the top oxide insulating layer. In order to provide enhanced device performance, a portion of the top oxide layer increases in thickness in a substantially continuous manner, while a portion of the lateral drift region beneath the top oxide layer decreases in thickness in a substantially continuous manner, both over a distance which is at least about a factor of five greater than the maximum thickness of the thin semiconductor film.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate and a Lateral Insulated Gate Bipolar Transistor (LIGBT) device in an SOI layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first and a body contact region of the second conductivity type in the body region and connected to the source region. A lateral drift region of a first conductivity type is provided adjacent the body region and forms a lightly-doped drain region, and a drain contact region of the first conductivity type is provided laterally spaced apart from the body region by the drift region with an anode region of the second conductivity type in the drain region and connected to the drain contact region.

Abstract: A silicon-on-insulator (SOI) hybrid transistor device structure includes a substrate, a buried insulating layer on the substrate, and a hybrid transistor device structure formed in a semiconductor surface layer on the buried insulating layer. The hybrid transistor device structure may advantageously include at least one MOS transistor structure and at least one conductivity modulation transistor structure electrically connected in parallel. In a particularly advantageous configuration, the MOS transistor structure may be an LDMOS transistor structure and the conductivity modulation transistor structure may be an LIGB transistor structure, with the hybrid transistor device being formed in a closed geometry configuration. This closed geometry configuration may have both substantially curved segments and substantially straight segments, with MOS structures being formed in the curved segments and conductivity modulation transistor structures being formed in the straight segments.

Abstract: A lateral thin-film Silicon-On-Insulator (SOI) PMOS device includes a semiconductor substrate, a buried insulating layer on the substrate and a lateral PMOS transistor device in an SOI layer on the buried insulating layer and having a source region of p-type conductivity formed in a body region of n-type conductivity. A lateral drift region of n-type conductivity is provided adjacent the body region, and a drain region of p-type conductivity is provided laterally spaced apart from the body region by the drift region. A gate electrode is provided over a part of the body region in which a channel region is formed during operation and extending over a part of the lateral drift region adjacent the body region, with the gate electrode being insulated from the body region and drift region by an insulation region.

Abstract: A method of forming a laterally-varying charge profile in a silicon carbide substrate includes the steps of forming a silicon nitride layer on a polysilicon layer formed on the silicon carbide substrate, and patterning the silicon nitride layer to provide a plurality of silicon nitrite layer segments which are spaced apart in the lateral direction and which are provided with openings therebetween which are of varying widths. The polysilicon layer is oxidized using the layer segments as an oxidation mask to form a silicon dioxide layer of varying thickness from the polysilicon layer and to form a polysilicon layer portion therebeneath of varying thickness. The silicon dioxide layer and silicon nitride layer segments are removed, and a dopant is ion implanted into the silicon carbide substrate using the polysilicon layer portion of varying thickness as an implantation mask to form a laterally-varying charge profile in the silicon carbide substrate.